公开(公告)号：US11923852B2

公开(公告)日：2024-03-05

申请号：US17487467

申请日：2021-09-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Prateek Mishra ,  Thanapandi G ,  Jagadeesh Anathahalli Singrigowda ,  Dhruvin Devangbhai Shah ,  Girish Anathahalli Singrigowda ,  Animesh Jain

IPC: H03K3/037 ,  H03K17/081 ,  H03K19/00

CPC classification number: H03K3/037 ,  H03K17/08104 ,  H03K19/0002

Abstract: A voltage level-shifting circuit for an integrated circuit includes an input terminal receiving a voltage signal referenced to an input/output (I/O) voltage level. A transistor overvoltage protection circuit includes a first p-type metal oxide semiconductor (PMOS) transistor includes a source coupled to the second voltage supply, a gate receiving an enable signal, and a drain connected to a central node. A first n-type metal oxide semiconductor (NMOS) transistor includes a drain connected to the central node, a gate connected to the input terminal, and a source connected to an output terminal. A second NMOS transistor includes a drain connected to the input terminal, a gate connected to the central node, and a source connected to the output terminal.

公开(公告)号：US20230098336A1

公开(公告)日：2023-03-30

申请号：US17487467

申请日：2021-09-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Prateek Mishra ,  Thanapandi G ,  Jagadeesh Anathahalli Singrigowda ,  Dhruvin Devangbhai Shah ,  Girish Anathahalli Singrigowda ,  Animesh Jain

IPC: H03K3/037 ,  H03K17/081 ,  H03K19/00

Abstract: A voltage level-shifting circuit for an integrated circuit includes an input terminal receiving a voltage signal referenced to an input/output (PO) voltage level. A transistor overvoltage protection circuit includes a first p-type metal oxide semiconductor (PMOS) transistor includes a source coupled to the second voltage supply, a gate receiving an enable signal, and a drain connected to a central node. A first n-type metal oxide semiconductor (NMOS) transistor includes a drain connected to the central node, a gate connected to the input terminal, and a source connected to an output terminal. A second NMOS transistor includes a drain connected to the input terminal, a gate connected to the central node, and a source connected to the output terminal.