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公开(公告)号：US20210183004A1
公开(公告)日：2021-06-17
申请号：US16713472
申请日：2019-12-13
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Todd MARTIN , Tad LITWILLER , Nishank PATHAK , Mangesh P. NIJASURE
IPC: G06T1/20 , H04L12/861 , H04L12/863
Abstract: A graphics processing unit (GPU) includes a packet management component that automatically aggregates data from input packets. In response to determining that a received first input packet does not indicate a send condition, and in response to determining that a generated output packet would be smaller than an output size threshold, the packet management component aggregates data corresponding to the first input packet with data corresponding to a second input packet stored at a packet buffer. In response to determining that a received third input packet indicates a send condition, the packet management component sends the aggregated data to a compute unit in an output packet and performs an operation indicated by the send condition.
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公开(公告)号：US20210374898A1
公开(公告)日：2021-12-02
申请号：US17318523
申请日：2021-05-12
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Mangesh P. NIJASURE , Tad LITWILLER , Todd MARTIN , Nishank PATHAK
Abstract: A graphics pipeline reduces the number of tessellation factors written to and read from a graphics memory. A hull shader stage of the graphics pipeline detects whether at least a threshold percentage of the tessellation factors for a thread group of patches are the same and, in some embodiments, whether at least the threshold percentage of the tessellation factors for a thread group of patches have a same value that either indicates that the plurality of patches are to be culled or that the plurality of patches are to be passed to a tessellator stage of the graphics pipeline. In response to detecting that at least the threshold percentage of the tessellation factors for the thread group are the same (or, additionally, that at least the threshold percentage of the tessellation factors have a value that either indicates that the plurality of patches are to be culled or that the plurality of patches are to be passed to a tessellator stage of the graphics pipeline), the hull shader stage bypasses writing at least a subset of the tessellation factors for the thread group of patches to the graphics memory, thus reducing bandwidth and increasing efficiency of the graphics pipeline.
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公开(公告)号：US20210295585A1
公开(公告)日：2021-09-23
申请号：US16825600
申请日：2020-03-20
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Saad ARRABI , Vishrut VAIBHAV , Mangesh P. NIJASURE , Todd MARTIN
IPC: G06T15/00
Abstract: A graphics pipeline includes a tessellator stage having a sub-patch distributor and a plurality of tessellators. The sub-patch distributor divides an input patch into a plurality of sub-primitive groups, with the primitive group limit governing the maximum permissible size for a given group of sub-primitives to be assigned to a tessellator. The sub-patch distributor recursively identifies a plurality of regions of the input patch, with the size and number of primitives of each region based on the specified primitive group limit. The sub-patch distributor assigns different regions to different sub-patch groups and distributes the sub-patch groups among the plurality of tessellators.
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Patent Agency Ranking
公开(公告)号：US20200174761A1
公开(公告)日：2020-06-04
申请号：US16227741
申请日：2018-12-20
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Brian J. FAVELA , Todd MARTIN , Robert A. GOTTLIEB
IPC: G06F8/41
Abstract: A method and system for compiler optimization includes analyzing a representation of source code to identify an original conditional construct having both a high-latency instruction and one or more instructions dependent on the high-latency instruction in a branch of the conditional construct. A set of one or more instructions following the conditional construct in the representation of source code and independent of the high-latency instruction is selected. An optimized representation of the source code is generated, whereby the optimized representation replaces the original conditional construct with a first split conditional construct positioned prior to the selected set of one or more instructions and a second split conditional construct positioned following the selected set of one or more instructions, The method further includes generating an executable representation of the source code based on the optimized representation of the source code.
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公开(公告)号：US20190164328A1
公开(公告)日：2019-05-30
申请号：US16238727
申请日：2019-01-03
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Anirudh R. ACHARYA , Swapnil SAKHARSHETE , Michael MANTOR , Mangesh P. NIJASURE , Todd MARTIN , Vineet GOEL
Abstract: Processing of non-real-time and real-time workloads is performed using discrete pipelines. A first pipeline includes a first shader and one or more fixed function hardware blocks. A second pipeline includes a second shader that is configured to emulate the at least one fixed function hardware block. First and second memory elements store first state information for the first pipeline and second state information for the second pipeline, respectively. A non-real-time workload executing in the first pipeline is preempted at a primitive boundary in response to a real-time workload being dispatched for execution in the second pipeline. The first memory element retains the first state information in response to preemption of the non-real-time workload. The first pipeline is configured to resume processing the subsequent primitive on the basis of the first state information stored in the first memory element.
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公开(公告)号：US20210150658A1
公开(公告)日：2021-05-20
申请号：US16683868
申请日：2019-11-14
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Mangesh P. NIJASURE , Tad LITWILLER , Todd MARTIN , Nishank PATHAK
Abstract: A graphics pipeline reduces the number of tessellation factors written to and read from a graphics memory. A hull shader stage of the graphics pipeline detects whether at least a threshold percentage of the tessellation factors for a thread group of patches are the same and, in some embodiments, whether at least the threshold percentage of the tessellation factors for a thread group of patches have a same value that either indicates that the plurality of patches are to be culled or that the plurality of patches are to be passed to a tessellator stage of the graphics pipeline. In response to detecting that at least the threshold percentage of the tessellation factors for the thread group are the same (or, additionally, that at least the threshold percentage of the tessellation factors have a value that either indicates that the plurality of patches are to be culled or that the plurality of patches are to be passed to a tessellator stage of the graphics pipeline), the hull shader stage bypasses writing at least a subset of the tessellation factors for the thread group of patches to the graphics memory, thus reducing bandwidth and increasing efficiency of the graphics pipeline.
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公开(公告)号：US20190318527A1
公开(公告)日：2019-10-17
申请号：US16452831
申请日：2019-06-26
Applicant: Advanced Micro Devices, Inc.
Inventor： Mangesh P. NIJASURE , Todd MARTIN , Michael MANTOR
Abstract: Improvements in the graphics processing pipeline that allow multiple pipelines to cooperate to render a single frame are disclosed. Two approaches are provided. In a first approach, world-space pipelines for the different graphics processing pipelines process all work for draw calls received from a central processing unit (CPU). In a second approach, the world-space pipelines divide up the work. Work that is divided is synchronized and redistributed at various points in the world-space pipeline. In either approach, the triangles output by the world-space pipelines are distributed to the screen-space pipelines based on the portions of the render surface overlapped by the triangles. Triangles are rendered by screen-space pipelines associated with the render surface portions overlapped by those triangles.
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公开(公告)号：US20200035017A1
公开(公告)日：2020-01-30
申请号：US16591287
申请日：2019-10-02
Applicant: Advanced Micro Devices, Inc.
Inventor： Mangesh P. NIJASURE , Randy W. RAMSEY , Todd MARTIN
Abstract: Improvements to graphics processing pipelines are disclosed. More specifically, the vertex shader stage, which performs vertex transformations, and the hull or geometry shader stages, are combined. If tessellation is disabled and geometry shading is enabled, then the graphics processing pipeline includes a combined vertex and graphics shader stage. If tessellation is enabled, then the graphics processing pipeline includes a combined vertex and hull shader stage. If tessellation and geometry shading are both disabled, then the graphics processing pipeline does not use a combined shader stage. The combined shader stages improve efficiency by reducing the number of executing instances of shader programs and associated resources reserved.
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