公开(公告)号：US20130232385A1

公开(公告)日：2013-09-05

申请号：US13863965

申请日：2013-04-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Kay Hesse ,  Suresh Periyacheri

IPC: G11C29/38

CPC classification number: G11C29/38 ,  G11C29/02 ,  G11C29/023 ,  G11C29/12 ,  G11C29/50 ,  G11C29/50012

Abstract: In a complex semiconductor device including embedded memories, the round trip latency may be determined during a memory self-test by applying a ping signal having the same latency as control and failure signals used during the self-test. The ping signal may be used for controlling an operation counter in order to obtain a reliable correspondence between the counter value and a memory operation causing a specified memory failure.

Abstract translation: 在包括嵌入式存储器的复杂半导体器件中，可以在存储器自检期间通过应用与在自检期间使用的控制和故障信号具有相同等待时间的ping信号来确定往返延迟。 ping信号可以用于控制操作计数器，以便获得计数器值与导致指定的存储器故障的存储器操作之间的可靠对应关系。

公开(公告)号：US09245652B2

公开(公告)日：2016-01-26

申请号：US13863965

申请日：2013-04-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Kay Hesse ,  Suresh Periyacheri

IPC: G11C29/38 ,  G11C29/02 ,  G11C29/12 ,  G11C29/50

CPC classification number: G11C29/38 ,  G11C29/02 ,  G11C29/023 ,  G11C29/12 ,  G11C29/50 ,  G11C29/50012

Abstract: In a complex semiconductor device including embedded memories, the round trip latency may be determined during a memory self-test by applying a ping signal having the same latency as control and failure signals used during the self-test. The ping signal may be used for controlling an operation counter in order to obtain a reliable correspondence between the counter value and a memory operation causing a specified memory failure.

公开(公告)号：US20130205179A1

公开(公告)日：2013-08-08

申请号：US13839621

申请日：2013-03-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Wei-Yu Chen ,  Kevin Badgett ,  Kay Hesse

IPC: G11C29/36

CPC classification number: G11C29/36 ,  G11C29/06 ,  G11C29/28 ,  G11C2029/2602

Abstract: Integrated circuits with memory built-in self test (MBIST) circuitry and methods are disclosed that employ enhanced features. In one aspect of the invention, an integrated circuit is provided having MIBST circuitry configured to serially test multiple arrays of memory elements within a component of the integrated circuit and to also conduct parallel initialization of the serially tested arrays. In another aspect of the invention, the MBST circuitry is used set the memory elements of the arrays to a first state and then to an inverse state during a burn-in operation to maintain each of the two opposing states for a desired time in order to either force a failure of the integrated circuit component or produce a pre-stressed component beyond an infancy stage.

Abstract translation: 具有存储器内置自检（MBIST）电路和方法的集成电路被公开，其采用增强的特征。 在本发明的一个方面，提供了一种集成电路，其具有MBIST电路，其被配置为串行测试集成电路的部件内的多个存储元件阵列，并且还对串行测试阵列进行并行初始化。 在本发明的另一方面，使用MBIST电路将阵列的存储元件设置为第一状态，然后在老化操作期间将其置于反向状态，以将两个相对状态中的每一个保持期望的时间，以便 要么强制集成电路部件的故障或者产生超过初级阶段的预应力部件。

公开(公告)号：US08639994B2

公开(公告)日：2014-01-28

申请号：US13839621

申请日：2013-03-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Wei-Yu Chen ,  Kevin Badgett ,  Kay Hesse

IPC: G01R31/28

CPC classification number: G11C29/36 ,  G11C29/06 ,  G11C29/28 ,  G11C2029/2602

Abstract: Integrated circuits with memory built-in self test (MBIST) circuitry and methods are disclosed that employ enhanced features. In one aspect of the invention, an integrated circuit is provided having MIBST circuitry configured to serially test multiple arrays of memory elements within a component of the integrated circuit and to also conduct parallel initialization of the serially tested arrays. In another aspect of the invention, the MBST circuitry is used set the memory elements of the arrays to a first state and then to an inverse state during a burn-in operation to maintain each of the two opposing states for a desired time in order to either force a failure of the integrated circuit component or produce a pre-stressed component beyond an infancy stage.

Abstract translation: 具有存储器内置自检（MBIST）电路和方法的集成电路被公开，其采用增强的特征。 在本发明的一个方面，提供了一种集成电路，其具有MBIST电路，其被配置为串行测试集成电路的部件内的多个存储元件阵列，并且还对串行测试阵列进行并行初始化。 在本发明的另一方面，使用MBIST电路将阵列的存储元件设置为第一状态，然后在老化操作期间将其置于反向状态，以将两个相对状态中的每一个保持期望的时间，以便 要么强制集成电路部件的故障或者产生超过初级阶段的预应力部件。