公开(公告)号：US20210407617A1

公开(公告)日：2021-12-30

申请号：US17027983

申请日：2020-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell Schreiber ,  Keith A. Kasprak ,  Vance Threatt ,  James A. Wingfield ,  William A. Halliday ,  Srinivas R. Sathu ,  Arijit Banerjee

IPC: G11C29/44 ,  G11C29/12 ,  G11C7/12 ,  G06F12/0811

Abstract: An integrated circuit includes a memory core and a built-in self-test (BIST) controller. The memory core has an array of memory cells located at intersections of a plurality of word lines and a plurality of bit line pairs. The BIST controller is coupled to the memory core and has a mission mode and a built-in self-test mode. When in the mission mode, the BIST controller performs read and write accesses using precharge on demand. When in the built-in self-test mode, the BIST controller performs a floating bit line test by draining a voltage on true and complement bit lines of a selected bit line pair and subsequently precharging the true and complement bit lines of the selected bit line pair, before reading or writing data using the true and complement bit lines of the selected bit line pair.

公开(公告)号：US11610879B2

公开(公告)日：2023-03-21

申请号：US16226311

申请日：2018-12-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell J. Schreiber ,  Richard M. Born ,  Carl D. Dietz ,  William A. Halliday

IPC: H01L27/02 ,  H03K19/00 ,  H01L23/495 ,  H01L25/04 ,  G06F1/26 ,  H01L23/498

Abstract: A handshake mechanism allows die discovery in a stacked die architecture that keeps inputs isolated until the handshake is complete. Power good indications are used as handshake signals between the die. A die keeps inputs isolated from above until a power good indication from the die above indicates presence of the die above. The die keeps inputs isolated from below until the die detects power is good and receives a power good indication from the die and the die below. In an implementation drivers and receivers, apart from configuration bus drivers and receivers are disabled until a fuse distribution done signal indicates that repairs have been completed. Drivers are then enabled and after a delay to ensure signals are driven, receivers are deisolated. A top die in the die stack never sees a power good indication from a die above and therefore keeps inputs from above isolated. That allows the height of the die stack to be unknown at power on.

公开(公告)号：US11264115B2

公开(公告)日：2022-03-01

申请号：US17027983

申请日：2020-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell Schreiber ,  Keith A. Kasprak ,  Vance Threatt ,  James A. Wingfield ,  William A. Halliday ,  Srinivas R. Sathu ,  Arijit Banerjee

IPC: G11C29/44 ,  G11C29/12 ,  G11C7/12 ,  G06F12/0811

Abstract: An integrated circuit includes a memory core and a built-in self-test (BIST) controller. The memory core has an array of memory cells located at intersections of a plurality of word lines and a plurality of bit line pairs. The BIST controller is coupled to the memory core and has a mission mode and a built-in self-test mode. When in the mission mode, the BIST controller performs read and write accesses using precharge on demand. When in the built-in self-test mode, the BIST controller performs a floating bit line test by draining a voltage on true and complement bit lines of a selected bit line pair and subsequently precharging the true and complement bit lines of the selected bit line pair, before reading or writing data using the true and complement bit lines of the selected bit line pair.