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公开(公告)号：US20230032375A1
公开(公告)日：2023-02-02
申请号：US17390293
申请日：2021-07-30
发明人： Eric Busta , Michael L. Golden , Sean M. O'Mullan , James Wingfield , Keith A. Kasprak , Russell Schreiber , Michael Estlick
摘要： An integrated circuit includes one or more processing units that execute instructions that employ a register file, control logic creates a pre-startup register free list, prior to normal operation of at least one of the processing units, that includes a list of registers devoid of undefective registers. In some implementations, no column and row repair information is provided to register file repair logic. In certain examples, the register file is configured as a repair-less register file. During normal operation of the one or more processing units, the integrated circuit employs the pre-startup register free list to select registers in a register file for the executing instructions. Associated methods are also presented.
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公开(公告)号：US20210407617A1
公开(公告)日：2021-12-30
申请号：US17027983
申请日：2020-09-22
发明人： Russell Schreiber , Keith A. Kasprak , Vance Threatt , James A. Wingfield , William A. Halliday , Srinivas R. Sathu , Arijit Banerjee
IPC分类号： G11C29/44 , G11C29/12 , G11C7/12 , G06F12/0811
摘要： An integrated circuit includes a memory core and a built-in self-test (BIST) controller. The memory core has an array of memory cells located at intersections of a plurality of word lines and a plurality of bit line pairs. The BIST controller is coupled to the memory core and has a mission mode and a built-in self-test mode. When in the mission mode, the BIST controller performs read and write accesses using precharge on demand. When in the built-in self-test mode, the BIST controller performs a floating bit line test by draining a voltage on true and complement bit lines of a selected bit line pair and subsequently precharging the true and complement bit lines of the selected bit line pair, before reading or writing data using the true and complement bit lines of the selected bit line pair.
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公开(公告)号：US20140204658A1
公开(公告)日：2014-07-24
申请号：US13749672
申请日：2013-01-24
发明人： John J. Wuu , Keith A. Kasprak , Russell Schreiber
IPC分类号： G11C11/412 , G11C7/00
CPC分类号： G11C11/412 , G11C7/04
摘要： An apparatus may comprise a memory cell configured to operate according to a voltage mode, a voltage controller coupled with the memory cell, wherein the voltage controller is configured to change the voltage mode of the memory cell between a low voltage mode and a high voltage mode, and a memory controller module coupled with the memory cell, wherein the memory controller is configured to invert a logic state stored in the memory cell based on the voltage mode.
摘要翻译： 装置可以包括被配置为根据电压模式操作的存储单元，与存储单元耦合的电压控制器，其中电压控制器被配置为在低电压模式和高电压模式之间改变存储单元的电压模式 以及与所述存储器单元耦合的存储器控制器模块，其中所述存储器控制器被配置为基于所述电压模式反转存储在所述存储器单元中的逻辑状态。
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公开(公告)号：US11907070B2
公开(公告)日：2024-02-20
申请号：US17390293
申请日：2021-07-30
发明人： Eric Busta , Michael L. Golden , Sean M. O′Mullan , James Wingfield , Keith A. Kasprak , Russell Schreiber , Michael Estlick
CPC分类号： G06F11/1417 , G06F9/3013 , G06F9/5011 , G06F11/0772
摘要： An integrated circuit includes one or more processing units that execute instructions that employ a register file, control logic creates a pre-startup register free list, prior to normal operation of at least one of the processing units, that includes a list of registers devoid of defective registers. In some implementations, no column and row repair information is provided to register file repair logic. In certain examples, the register file is configured as a repair-less register file. During normal operation of the one or more processing units, the integrated circuit employs the pre-startup register free list to select registers in a register file for the executing instructions. Associated methods are also presented.
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公开(公告)号：US10438636B2
公开(公告)日：2019-10-08
申请号：US15834644
申请日：2017-12-07
发明人： Tawfik Ahmed , Amlan Ghosh , Keith A. Kasprak , Ricardo Cantu
IPC分类号： G11C7/12 , H01L23/522 , G11C7/10 , G11C5/06
摘要： Write assist circuitry facilitates increased voltage applied to a memory device such as a memory cell or bitcell in changing a logical state of the memory device during a write operation. The write assist circuitry includes a second capacitive line or “metal cap” in addition to a first capacitive line coupled to one of a pair of bitlines to which voltage may be selectively applied. The capacitive lines provide increased write assistance to the memory device. The second capacitive line structurally lies in a second orientation and is formed in an integrated circuit second metal layer relative to the first capacitive line in some embodiments. The additional capacitive line provides negative bitline assistance by selectively driving its corresponding bitlines to be negative during a write operation.
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公开(公告)号：US08958236B2
公开(公告)日：2015-02-17
申请号：US13749672
申请日：2013-01-24
发明人： John J. Wuu , Keith A. Kasprak , Russell Schreiber
IPC分类号： G11C7/00 , G11C11/412 , G11C7/04
CPC分类号： G11C11/412 , G11C7/04
摘要： An apparatus may comprise a memory cell configured to operate according to a voltage mode, a voltage controller coupled with the memory cell, wherein the voltage controller is configured to change the voltage mode of the memory cell between a low voltage mode and a high voltage mode, and a memory controller module coupled with the memory cell, wherein the memory controller is configured to invert a logic state stored in the memory cell based on the voltage mode.
摘要翻译： 装置可以包括被配置为根据电压模式操作的存储单元，与存储单元耦合的电压控制器，其中电压控制器被配置为在低电压模式和高电压模式之间改变存储单元的电压模式 以及与所述存储器单元耦合的存储器控制器模块，其中所述存储器控制器被配置为基于所述电压模式反转存储在所述存储器单元中的逻辑状态。
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公开(公告)号：US20230100607A1
公开(公告)日：2023-03-30
申请号：US17488519
申请日：2021-09-29
IPC分类号： G11C11/419
摘要： A technique reduces power consumption of a bit cell in a memory and provides write assistance to the bit cell. When the bit cell is active, a power-saving write-assist circuit coupled to the bit cell is selectively sized according to a type of memory access. When the bit cell is inactive, the virtual power supply node floats to a predetermined voltage between a first voltage on a first power supply node coupled to the bit cell and a second voltage on a second power supply node coupled to the bit cell. A method for controlling power consumption of a bit cell and assisting a write to the bit cell includes providing a reference voltage to a virtual power supply node coupled to the bit cell. The reference voltage is provided based on an operational state of the bit cell and a type of memory access to the bit cell.
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公开(公告)号：US11264115B2
公开(公告)日：2022-03-01
申请号：US17027983
申请日：2020-09-22
发明人： Russell Schreiber , Keith A. Kasprak , Vance Threatt , James A. Wingfield , William A. Halliday , Srinivas R. Sathu , Arijit Banerjee
IPC分类号： G11C29/44 , G11C29/12 , G11C7/12 , G06F12/0811
摘要： An integrated circuit includes a memory core and a built-in self-test (BIST) controller. The memory core has an array of memory cells located at intersections of a plurality of word lines and a plurality of bit line pairs. The BIST controller is coupled to the memory core and has a mission mode and a built-in self-test mode. When in the mission mode, the BIST controller performs read and write accesses using precharge on demand. When in the built-in self-test mode, the BIST controller performs a floating bit line test by draining a voltage on true and complement bit lines of a selected bit line pair and subsequently precharging the true and complement bit lines of the selected bit line pair, before reading or writing data using the true and complement bit lines of the selected bit line pair.
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公开(公告)号：US20200335142A1
公开(公告)日：2020-10-22
申请号：US16454692
申请日：2019-06-27
IPC分类号： G11C7/06 , G11C11/419 , G11C11/412 , H01L27/11
摘要： A circuit includes a repeating series of first circuits and a repeating series of second circuits placed next to the repeating series of first circuits and interacts with corresponding portions of the first circuits in the series. The repeating series of second circuits is formed in diffusion regions and diffusion wells which extend along the direction in which the second circuits repeat. The repeating series of the first and second circuits is interrupted by at least one dummy circuit region, which occupies the space of one or more instances of the first and second repeating series. The dummy circuit region also includes taps for biasing the diffusion regions and diffusion wells of the second circuits.
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