公开(公告)号：US10073785B2

公开(公告)日：2018-09-11

申请号：US15180806

申请日：2016-06-13

Applicant: Advanced Micro Devices, Inc.

Inventor： William Evan Jones, III

IPC: G06F12/08 ,  G06F12/0862 ,  G06F12/0842

CPC classification number: G06F12/0862 ,  G06F12/0842 ,  G06F2212/1021 ,  G06F2212/502 ,  G06F2212/6026

Abstract: In a processing system comprising a cache, a method includes monitoring demand cache accesses for a thread to maintain a first running count of a number of times demand cache accesses for the thread are directed to cachelines that are adjacent in a first direction to cachelines that are targets of a set of sampled cache accesses for the thread. In response to determining the first running count has exceeded a first threshold, the method further includes enabling a first prefetching mode in which a received demand cache access for the thread triggers a prefetch request for a cacheline adjacent in the first direction to a cacheline targeted by the received demand cache access.

公开(公告)号：US20180018266A1

公开(公告)日：2018-01-18

申请号：US15212863

申请日：2016-07-18

Applicant: Advanced Micro Devices, Inc.

Inventor： William Evan Jones, III

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F12/0811 ,  G06F2212/1016 ,  G06F2212/6026

Abstract: A processing system includes a cache and a prefetcher to prefetch lines from a memory into the cache. The prefetcher receives a memory access request to a first address in the memory and sets a stride length associated with an instruction that issued the memory access request to a length of a line in the cache. The stride length indicates a number of bytes between addresses of lines that are prefetched from the memory into the cache.

公开(公告)号：US09892063B2

公开(公告)日：2018-02-13

申请号：US13686588

申请日：2012-11-27

Applicant: Advanced Micro Devices, Inc.

Inventor： William Evan Jones, III

IPC: G06F13/00 ,  G06F12/14 ,  G06F9/52 ,  G06F13/16

CPC classification number: G06F12/1441 ,  G06F9/526 ,  G06F12/1458 ,  G06F13/1673 ,  G06F2209/521

Abstract: In response to a processor receiving data associated with a shared memory location, a contention blocking buffer stores a memory address of the shared memory location. In response to a probe seeking to take ownership of the shared memory location, the contention blocking buffer determines if the memory address indicated by the probe is stored at the contention blocking buffer. If so, the contention blocking buffer blocks the probe, thereby preventing another processor from taking ownership of the shared memory location.

公开(公告)号：US20170357587A1

公开(公告)日：2017-12-14

申请号：US15180806

申请日：2016-06-13

Applicant: Advanced Micro Devices, Inc.

Inventor： William Evan Jones, III

IPC: G06F12/0862 ,  G06F12/0842

CPC classification number: G06F12/0862 ,  G06F12/0842 ,  G06F2212/1021 ,  G06F2212/502 ,  G06F2212/6026

Abstract: In a processing system comprising a cache, a method includes monitoring demand cache accesses for a thread to maintain a first running count of a number of times demand cache accesses for the thread are directed to cachelines that are adjacent in a first direction to cachelines that are targets of a set of sampled cache accesses for the thread. In response to determining the first running count has exceeded a first threshold, the method further includes enabling a first prefetching mode in which a received demand cache access for the thread triggers a prefetch request for a cacheline adjacent in the first direction to a cacheline targeted by the received demand cache access.

公开(公告)号：US20140149703A1

公开(公告)日：2014-05-29

申请号：US13686588

申请日：2012-11-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： William Evan Jones, III

IPC: G06F12/14

CPC classification number: G06F12/1441 ,  G06F9/526 ,  G06F12/1458 ,  G06F13/1673 ,  G06F2209/521

Abstract: In response to a processor receiving data associated with a shared memory location, a contention blocking buffer stores a memory address of the shared memory location. In response to a probe seeking to take ownership of the shared memory location, the contention blocking buffer determines if the memory address indicated by the probe is stored at the contention blocking buffer. If so, the contention blocking buffer blocks the probe, thereby preventing another processor from taking ownership of the shared memory location.

Abstract translation: 响应于处理器接收与共享存储器位置相关联的数据，争用阻止缓冲器存储共享存储器位置的存储器地址。 响应于寻求获得共享存储器位置的所有权的探测器，争用阻止缓冲器确定由探测器指示的存储器地址是否存储在争用阻止缓冲器中。 如果是这样，则争用阻塞缓冲器阻止探测器，从而防止另一处理器获取共享存储器位置的所有权。