公开(公告)号：US10360177B2

公开(公告)日：2019-07-23

申请号：US15189054

申请日：2016-06-22

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Syed Zohaib M. Gilani ,  Jiasheng Chen ,  QingCheng Wang ,  YunXiao Zou ,  Michael Mantor ,  Bin He ,  Timour T. Paltashev

IPC: G06F15/80 ,  G06F1/3234 ,  G06T15/00

Abstract: Described is a method and processing apparatus to improve power efficiency by gating redundant threads processing. In particular, the method for gating redundant threads in a graphics processor includes determining if data for a thread and data for at least another thread are within a predetermined similarity threshold, gating execution of the at least another thread if the data for the thread and the data for the at least another thread are within the predetermined similarity threshold, and using an output data from the thread as an output data for the at least another thread.

公开(公告)号：US20170371393A1

公开(公告)日：2017-12-28

申请号：US15189054

申请日：2016-06-22

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Syed Zohaib M. Gilani ,  Jiasheng Chen ,  QingCheng Wang ,  YunXiao Zou ,  Michael Mantor ,  Bin He ,  Timour T. Paltashev

IPC: G06F1/32 ,  G06F15/80

CPC classification number: G06F15/8007 ,  G06F1/3234 ,  G06F1/3243 ,  G06T15/005 ,  Y02D10/152

Abstract: Described is a method and processing apparatus to improve power efficiency by gating redundant threads processing. In particular, the method for gating redundant threads in a graphics processor includes determining if data for a thread and data for at least another thread are within a predetermined similarity threshold, gating execution of the at least another thread if the data for the thread and the data for the at least another thread are within the predetermined similarity threshold, and using an output data from the thread as an output data for the at least another thread.

公开(公告)号：US11494192B2

公开(公告)日：2022-11-08

申请号：US16860842

申请日：2020-04-28

Applicant: ADVANCED MICRO DEVICES, INC. ,  ADVANCED MICRO DEVICES (SHANGHAI) CO., LTD.

Inventor： Jiasheng Chen ,  YunXiao Zou ,  Bin He ,  Angel E. Socarras ,  QingCheng Wang ,  Wei Yuan ,  Michael Mantor

IPC: G06F9/38 ,  G06F9/30 ,  G06F15/80 ,  G06F15/76

Abstract: A processing element is implemented in a stage of a pipeline and configured to execute an instruction. A first array of multiplexers is to provide information associated with the instruction to the processing element in response to the instruction being in a first set of instructions. A second array of multiplexers is to provide information associated with the instruction to the first processing element in response to the instruction being in a second set of instructions. A control unit is to gate at least one of power or a clock signal provided to the first array of multiplexers in response to the instruction being in the second set.

公开(公告)号：US10656951B2

公开(公告)日：2020-05-19

申请号：US15789318

申请日：2017-10-20

Applicant: Advanced Micro Devices, Inc. ,  Advanced Micro Devices (Shanghai) Co., Ltd.

Inventor： Jiasheng Chen ,  YunXiao Zou ,  Bin He ,  Angel E. Socarras ,  QingCheng Wang ,  Wei Yuan ,  Michael Mantor

IPC: G06F9/30 ,  G06F9/38 ,  G06F15/80 ,  G06F15/76

Abstract: A processing element is implemented in a stage of a pipeline and configured to execute an instruction. A first array of multiplexers is to provide information associated with the instruction to the processing element in response to the instruction being in a first set of instructions. A second array of multiplexers is to provide information associated with the instruction to the first processing element in response to the instruction being in a second set of instructions. A control unit is to gate at least one of power or a clock signal provided to the first array of multiplexers in response to the instruction being in the second set.