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    Compressing texture data on a per-channel basis
    4.
    发明授权
    Compressing texture data on a per-channel basis 有权

    公开(公告)号：US11694367B2

    公开(公告)日：2023-07-04

    申请号：US17716186

    申请日：2022-04-08

    Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

    Inventor： Saurabh Sharma ,  Laurent Lefebvre ,  Sagar Shankar Bhandare ,  Ruijin Wu

    IPC: G06T9/00 ,  G06T1/60

    CPC classification number: G06T9/00 ,  G06T1/60 ,  G06T2200/04

    Abstract: Sampling circuitry independently accesses channels of texture data that represent a set of pixels. One or more processing units separately compress the channels of the texture data and store compressed data representative of the channels of the texture data for the set of pixels. The channels can include a red channel, a blue channel, and a green channel that represent color values of the set of pixels and an alpha channel that represents degrees of transparency of the set of pixels. Storing the compressed data can include writing the compress data to portions of a cache. The processing units can identify a subset of the set of pixels that share a value of a first channel of the plurality of channels and represent the value of the first channel over the subset of the set of pixels using information representing the value, the first channel, and boundaries of the subset.

    COMPRESSING TEXTURE DATA ON A PER-CHANNEL BASIS
    5.
    发明申请
    COMPRESSING TEXTURE DATA ON A PER-CHANNEL BASIS 有权

    公开(公告)号：US20230048839A1

    公开(公告)日：2023-02-16

    申请号：US17716186

    申请日：2022-04-08

    Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

    Inventor： Saurabh SHARMA ,  Laurent Lefebvre ,  Sager Shankar Bhandare ,  Ruijin Wu

    IPC: G06T9/00 ,  G06T1/60

    Abstract: Sampling circuitry independently accesses channels of texture data that represent a set of pixels. One or more processing units separately compress the channels of the texture data and store compressed data representative of the channels of the texture data for the set of pixels. The channels can include a red channel, a blue channel, and a green channel that represent color values of the set of pixels and an alpha channel that represents degrees of transparency of the set of pixels. Storing the compressed data can include writing the compress data to portions of a cache. The processing units can identify a subset of the set of pixels that share a value of a first channel of the plurality of channels and represent the value of the first channel over the subset of the set of pixels using information representing the value, the first channel, and boundaries of the subset.

    Compressing texture data on a per-channel basis
    7.
    发明授权
    Compressing texture data on a per-channel basis 有权

    公开(公告)号：US11308648B2

    公开(公告)日：2022-04-19

    申请号：US17030048

    申请日：2020-09-23

    Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

    Inventor： Saurabh Sharma ,  Laurent Lefebvre ,  Sagar Shankar Bhandare ,  Ruijin Wu

    IPC: G06T9/00 ,  G06T1/60

    Abstract: Sampling circuitry independently accesses channels of texture data that represent a set of pixels. One or more processing units separately compress the channels of the texture data and store compressed data representative of the channels of the texture data for the set of pixels. The channels can include a red channel, a blue channel, and a green channel that represent color values of the set of pixels and an alpha channel that represents degrees of transparency of the set of pixels. Storing the compressed data can include writing the compress data to portions of a cache. The processing units can identify a subset of the set of pixels that share a value of a first channel of the plurality of channels and represent the value of the first channel over the subset of the set of pixels using information representing the value, the first channel, and boundaries of the subset.

    Temporal foveated rendering using motion estimation
    9.
    发明授权
    Temporal foveated rendering using motion estimation 有权

    公开(公告)号：US10169843B1

    公开(公告)日：2019-01-01

    申请号：US15818072

    申请日：2017-11-20

    Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

    Inventor： Ihab Amer ,  Guennadi Riguer ,  Ruijin Wu ,  Skyler J. Saleh ,  Boris Ivanovic ,  Gabor Sines

    IPC: G06T3/40 ,  G06T7/136 ,  G06T7/13 ,  G06T7/246

    Abstract: A processing system selectively renders pixels or blocks of pixels of an image and leaves some pixels or blocks of pixels unrendered to conserve resources. The processing system generates a motion vector field to identify regions of an image having moving areas. The processing system uses a rendering processor to identify as regions of interest those units having little to no motion, based on the motion vector field, and a large amount of edge activity, and to minimize the probability of unrendered pixels, or “holes”, in these regions. To avoid noticeable patterns, the rendering processor applies a probability map to determine the possible locations of holes, assigning to each unit a probability indicating the percentage of pixels within the unit that will be holes, and assigning a lower probability to units identified as regions of interest.

    Processing system with selective priority-based two-level binning
    10.
    发明授权
    Processing system with selective priority-based two-level binning 有权

    公开(公告)号：US12266030B2

    公开(公告)日：2025-04-01

    申请号：US17231425

    申请日：2021-04-15

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Anirudh R. Acharya ,  Ruijin Wu ,  Young In Yeo

    IPC: G06T1/20 ,  G06F9/50 ,  G06T7/11

    Abstract: Systems and methods related to priority-based and performance-based selection of a render mode, such as a two-level binning mode, in which to execute workloads with a graphics processing unit (GPU) of a system are provided. A user mode driver (UMD) or kernel mode driver (KMD) executed at a central processing unit (CPU) configures low and medium priority workloads to be executed in a two-level binning mode and selects a binning mode for high priority workloads based on whether performance heuristics indicate that one or more binning conditions or override conditions have been met. High priority workloads are maintained in a high priority queue, while low and medium priority workloads are maintained in a low/medium priority queue, such that execution of low and medium priority workloads at the GPU can be preempted in favor of executing high priority workloads.

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