公开(公告)号：US12027469B2

公开(公告)日：2024-07-02

申请号：US17500920

申请日：2021-10-13

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： En Hao Hsu ,  Kuo Hwa Tzeng ,  Chia-Pin Chen ,  Chi Long Tsai

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/16

CPC classification number: H01L23/562 ,  H01L23/16 ,  H01L23/3107 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/022 ,  H01L2224/02377 ,  H01L2224/13018

Abstract: An electronic device package and manufacturing method thereof are provided. The electronic device package includes an electronic component including an active surface, a patterned conductive layer disposed on the active surface, an encapsulation layer disposed over the patterned conductive layer, and a buffer layer disposed between the patterned conductive layer and the encapsulation layer. The buffer layer is shaped and sized to alleviate a stress generated due to an interaction between the patterned conductive layer and the encapsulation layer.

公开(公告)号：US11798859B2

公开(公告)日：2023-10-24

申请号：US17317762

申请日：2021-05-11

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chia-Pin Chen ,  Chia-Sheng Tien ,  Wan-Ting Chiu ,  Chi Long Tsai

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L25/18 ,  H01L25/065

CPC classification number: H01L23/3135 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/24146 ,  H01L2224/24175 ,  H01L2224/24265 ,  H01L2224/25171 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06572

Abstract: An electronic device package includes an encapsulated electronic component, a substrate, a conductor and a buffer layer. The encapsulated electronic component includes a redistribution layer (RDL) and an encapsulation layer. The first surface is closer to the RDL than the second surface is. The encapsulation layer includes a first surface, and a second surface opposite to the first surface. The substrate is disposed on the second surface of the encapsulation layer. The conductor is disposed between the substrate and the encapsulated electronic component, and electrically connecting the substrate to the encapsulated electronic component. The buffer layer is disposed between the substrate and the encapsulated electronic component and around the conductor.

公开(公告)号：US12183593B2

公开(公告)日：2024-12-31

申请号：US17332854

申请日：2021-05-27

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chia-Pin Chen ,  Chia Sheng Tien ,  Wan-Ting Chiu ,  Chi Long Tsai ,  Cyuan-Hong Shih ,  Yen Liang Chen

IPC: H01L21/48 ,  H01L23/00 ,  H01L25/00

Abstract: A manufacturing method for manufacturing a package structure is provided. The manufacturing method includes: (a) providing a carrier having a top surface and a lateral side surface, wherein the top surface includes a main portion and a flat portion connecting the lateral side surface, and a first included angle between the main portion and the flat portion is less than a second included angle between the main portion and the lateral side surface; (b) forming an under layer on the carrier to at least partially expose the flat portion; and (c) forming a dielectric layer on the under layer and covering the exposed flat portion.

公开(公告)号：US11011444B2

公开(公告)日：2021-05-18

申请号：US16540837

申请日：2019-08-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ya-Yu Hsieh ,  Chin-Li Kao ,  Chung-Hsuan Tsai ,  Chia-Pin Chen

IPC: H01L23/29 ,  H01L23/00 ,  H01L23/31 ,  H01L21/66

Abstract: The present disclosure provides a semiconductor package structure having a semiconductor die having an active surface, a conductive bump on the active surface, configured to electrically couple the semiconductor die to an external circuit, the conductive bump having a bump height, a dielectric encapsulating the semiconductor die and the conductive bump, and a plurality of fillers in the dielectric, each of the fillers comprising a diameter, wherein a maximum diameter of the fillers is smaller than the bump height.