公开(公告)号：US09917043B2

公开(公告)日：2018-03-13

申请号：US15479074

申请日：2017-04-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien Lin Chang Chien ,  Chin-Li Kao ,  Chang Chi Lee ,  Chih-Pin Hung

IPC: H01L23/498 ,  H01L21/48 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/562 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/81193 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06586

Abstract: In one or more embodiments, a semiconductor package includes a redistribution layer, a conductive pad, a dielectric layer, a silicon layer, and a conductive contact. The redistribution layer includes a first surface and a second surface opposite to the first surface. The conductive pad is on the first surface of the redistribution layer. The dielectric layer is disposed on the first surface of the redistribution layer to cover a first portion of the conductive pad and to expose a second portion of the conductive pad. The silicon layer is disposed on the dielectric layer, the silicon layer having a recess to expose the second portion of the conductive pad. The conductive contact is disposed over the silicon layer and extends into the recess of the silicon layer.

公开(公告)号：US09589840B2

公开(公告)日：2017-03-07

申请号：US14274289

申请日：2014-05-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chin-Li Kao ,  Chang-Chi Lee ,  Yi-Shao Lai

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/367 ,  H01L23/525 ,  H01L23/532 ,  H01L23/13 ,  H01L23/14 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/06 ,  H01L2924/07025 ,  H01L2924/15738 ,  H01L2924/15763 ,  H01L2924/15787 ,  H01L2924/15798 ,  H01L2924/3511 ,  H01L2924/35121 ,  H01L2224/0401

Abstract: The present disclosure relates to a semiconductor package and a manufacturing method thereof. The semiconductor package includes a semiconductor element including a main body, a plurality of conductive vias, and at least one filler. The conductive vias penetrate through the main body. The filler is located in the main body, and a coefficient of thermal expansion (CTE) of the filler is different from that of the main body and the conductive vias. Thus, the CTE of the overall semiconductor element can be adjusted, so as to reduce warpage.

Abstract translation: 本公开涉及半导体封装及其制造方法。 半导体封装包括半导体元件，其包括主体，多个导电通孔和至少一个填料。 导电通孔穿过主体。 填料位于主体中，填料的热膨胀系数（CTE）与主体和导电通孔的热膨胀系数不同。 因此，可以调整整个半导体元件的CTE，以便减少翘曲。

公开(公告)号：US11855034B2

公开(公告)日：2023-12-26

申请号：US17334622

申请日：2021-05-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chung-Hung Lai ,  Chin-Li Kao ,  Chih-Yi Huang ,  Teck-Chong Lee

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L23/14 ,  H01L25/065

CPC classification number: H01L24/73 ,  H01L23/14 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16014 ,  H01L2224/16105 ,  H01L2224/16165 ,  H01L2224/16168 ,  H01L2224/73204 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1616 ,  H01L2924/16251 ,  H01L2924/182 ,  H01L2924/3511 ,  H01L2924/3512

Abstract: An electronic device package is provided. The electronic device package includes a redistribution layer (RDL), a first electronic component and an interconnector. The RDL includes a topmost circuit layer, and the topmost circuit layer includes a conductive trace. The first electronic component is disposed over the RDL. The interconnector is disposed between the RDL and the first electronic component. A direction is defined by extending from a center of the first electronic component toward an edge of the first electronic component, and the direction penetrates a first sidewall and a second sidewall of the interconnector, the second sidewall is farther from the center of the first electronic component than the first sidewall is, and the conductive trace is outside a projection region of the second sidewall.

公开(公告)号：US09773753B1

公开(公告)日：2017-09-26

申请号：US15356400

申请日：2016-11-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yuan-Ting Lin ,  Chi-Yu Wang ,  Wei-Hong Lai ,  Chin-Li Kao

IPC: H01L23/48 ,  H01L25/065 ,  H01L25/00 ,  H01L23/538 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/5389 ,  H01L21/568 ,  H01L23/3135 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2924/14 ,  H01L2924/3511

Abstract: A semiconductor device includes a first die, a second die, an encapsulant, a first dielectric layer, and at least one first trace. The first die includes a first surface and a second surface opposite to the first surface and includes at least one first pad disposed adjacent to the first surface of the first die. The second die includes a first surface and a second surface opposite to the first surface and includes at least one second pad disposed adjacent to the first surface of the second die. The first dielectric layer is disposed on at least a portion of the first surface of the first die and at least a portion of the first surface of the second die. The first trace is disposed on the first dielectric layer, which connects the first pad to the second pad, and the first trace comprises an end portion disposed adjacent to the first pad and a body portion, and the end portion extends at an angle θ1 relative to a direction of extension of the body portion.

公开(公告)号：US09589871B2

公开(公告)日：2017-03-07

申请号：US14685529

申请日：2015-04-13

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tang-Yuan Chen ,  Chin-Li Kao ,  Kuo-Hua Chen ,  Ming-Hung Chen ,  Dao-Long Chen

IPC: H01L23/49 ,  H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49548 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49582 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/32245 ,  H01L2224/32502 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/83801 ,  H01L2224/83805 ,  H01L2224/92244 ,  H01L2924/15153 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00014

Abstract: The present disclosure relates to a semiconductor package structure and a method for manufacturing the same. The semiconductor package structure includes a leadframe and a semiconductor die. The leadframe includes a main portion and a protrusion portion. The semiconductor die is bonded to a first surface of the main portion. The protrusion portion protrudes from a second surface of the main portion. The position of the protrusion portion corresponds to the position of the semiconductor die.

Abstract translation: 本公开涉及一种半导体封装结构及其制造方法。 半导体封装结构包括引线框和半导体管芯。 引线框架包括主体部分和突出部分。 半导体管芯结合到主要部分的第一表面。 突出部分从主体部分的第二表面突出。 突起部分的位置对应于半导体管芯的位置。

公开(公告)号：US11430761B2

公开(公告)日：2022-08-30

申请号：US16793991

申请日：2020-02-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yun-Ching Hung ,  Yung-Sheng Lin ,  Chin-Li Kao

IPC: H01L23/00

Abstract: Present disclosure provides a semiconductor package, including a first substrate having a first active surface and a first trench recessed from the first active surface, a second substrate having a second trench facing the first trench, and a pathway cavity defined by the first trench and the second trench. The first trench comprises a first metal protrusion and a first insulating protrusion. A method for manufacturing the semiconductor package described herein is also disclosed.

公开(公告)号：US11244909B2

公开(公告)日：2022-02-08

申请号：US16817407

申请日：2020-03-12

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Fan-Yu Min ,  Chen-Hung Lee ,  Wei-Hang Tai ,  Yuan-Tzuo Luo ,  Wen-Yuan Chuang ,  Chun-Cheng Kuo ,  Chin-Li Kao

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

Abstract: A package structure and a manufacturing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The first electronic device is disposed on the wiring structure. The second electronic device is disposed on the wiring structure. The first electronic device and the second electronic device are disposed side by side. A gap between the first electronic device and the second electronic device is greater than or equal to about 150 μm.

公开(公告)号：US10037974B2

公开(公告)日：2018-07-31

申请号：US15416907

申请日：2017-01-26

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien Lin Chang Chien ,  Chang Chi Lee ,  Chin-Li Kao ,  Dao-Long Chen ,  Ta-Chien Cheng

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/367 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3672 ,  H01L24/16 ,  H01L24/33 ,  H01L24/81 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device package includes a package substrate, a first electronic device, a second electronic device and a first molding layer. The package substrate includes a first surface, a second surface opposite to the first surface, and an edge. The first electronic device is positioned over and electrically connected to the package substrate through the first surface. The second electronic device is positioned over and electrically connected to the first electronic device. The first molding layer is positioned over the package substrate, and the first molding layer encapsulates a portion of the first surface and the edge of the package substrate.

公开(公告)号：US20180128612A1

公开(公告)日：2018-05-10

申请号：US15862476

申请日：2018-01-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Seungbae Park ,  Yu-Ho Hsu ,  Chin-Li Kao ,  Tai-Yuan Huang

IPC: G01C11/04 ,  G01B11/245

CPC classification number: G01C11/04 ,  G01B11/245 ,  G01B2210/56

Abstract: The measurement equipment includes a rack, a first image capturing device, a second image capturing device, a third image capturing device and a fourth image capturing device. Wherein, the first image capturing device and the second image capturing device capture an entire image of a to-be-measured object, the third image capturing device and the fourth image capturing device capture a plurality of local images of a plurality of local areas of the to-be-measured object, and the entire image and the local images and are simultaneously captured.

公开(公告)号：US11309253B2

公开(公告)日：2022-04-19

申请号：US16858269

申请日：2020-04-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chin-Li Kao

IPC: H01L23/538 ,  H01L21/66 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: A package structure and a method for manufacturing a package structure are provided. The package structure includes a first conductive structure and a second conductive structure. The first conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The second conductive structure is bonded to the first conductive structure. The second conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. A distribution density of the circuit layer of the first conductive structure is greater than a distribution density of the circuit layer of the second conductive structure. A size of the second conductive structure is less than a size of the first conductive structure.