公开(公告)号：US10658319B2

公开(公告)日：2020-05-19

申请号：US16247437

申请日：2019-01-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Pin Hung ,  Dao-Long Chen ,  Ying-Ta Chiu ,  Ping-Feng Yang

IPC: H01L23/00

Abstract: A semiconductor device includes a semiconductor element, a trace disposed adjacent to a surface of the semiconductor element, a bonding pad disposed adjacent to the surface of the semiconductor element and connected to the trace, and a pillar disposed on the bonding pad. The pillar includes a first end wall, a second end wall opposite the first end wall, a first side wall, and a second side wall opposite the first side wall. The first side wall and the second side wall connect the first end wall to the second end wall. One or both of the first side wall and the second side wall incline inwardly from the first end wall to the second end wall. The pillar is disposed on the bonding pad such that the first end wall is closer to the trace than is the second end wall.

公开(公告)号：US10181448B2

公开(公告)日：2019-01-15

申请号：US15076831

申请日：2016-03-22

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Pin Hung ,  Dao-Long Chen ,  Ying-Ta Chiu ,  Ping-Feng Yang

IPC: H01L23/00

Abstract: A semiconductor device includes a semiconductor element, a trace disposed adjacent to a surface of the semiconductor element, a bonding pad disposed adjacent to the surface of the semiconductor element and connected to the trace, and a pillar disposed on the bonding pad. The pillar includes a first end wall, a second end wall opposite the first end wall, a first side wall, and a second side wall opposite the first side wall. The first side wall and the second side wall connect the first end wall to the second end wall. One or both of the first side wall and the second side wall incline inwardly from the first end wall to the second end wall. The pillar is disposed on the bonding pad such that the first end wall is closer to the trace than is the second end wall.

公开(公告)号：US09917071B1

公开(公告)日：2018-03-13

申请号：US15371889

申请日：2016-12-07

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ying-Ta Chiu ,  Yong-Da Chiu ,  Dao-Long Chen ,  Chih-Cheng Lee ,  Chih-Pin Hung

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L24/83 ,  H01L23/498 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/13017 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/16147 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/32147 ,  H01L2224/81385 ,  H01L2224/81898 ,  H01L2224/83139 ,  H01L2224/83895 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/3511 ,  H01L2224/81

Abstract: A semiconductor package includes: a first substrate including a first interconnection structure extending from a surface of the first substrate, the first interconnection structure including grains of a first size, a second substrate including: a second interconnection structure comprising grains of a second size, and a third interconnection structure disposed between the first interconnection structure and the second interconnection structure, the third interconnection structure including grains of a third size, a first sidewall inclined at a first angle to a reference plane and a second sidewall inclined at a second angle to the reference plane, wherein the first angle is different from the second angle, the first sidewall is disposed between the first substrate and the second sidewall, and the third size is smaller than both the first size and the second size.

公开(公告)号：US10096569B2

公开(公告)日：2018-10-09

申请号：US15444130

申请日：2017-02-27

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC. ,  NATIONAL CHUNG HSING UNIVERSITY

Inventor： Ying-Ta Chiu ,  Shang-Kun Huang ,  Yong-Da Chiu ,  Jenn-Ming Song

IPC: H01L23/00

Abstract: The present disclosure relates to a method for manufacturing a semiconductor device. The method includes providing a first electronic component including a first metal contact and a second electronic component including a second metal contact, changing a lattice of the first metal contact, and bonding the first metal contact to the second metal contact under a predetermined pressure and a predetermined temperature.

公开(公告)号：US09953930B1

公开(公告)日：2018-04-24

申请号：US15299236

申请日：2016-10-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ying-Ta Chiu ,  Chiu-Wen Lee ,  Dao-Long Chen ,  Po-Hsien Sung ,  Ping-Feng Yang ,  Kwang-Lung Lin

IPC: H01L21/00 ,  H01L23/10 ,  H01L23/552

CPC classification number: H01L23/60 ,  H01L21/56 ,  H01L21/565 ,  H01L23/06 ,  H01L23/10 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/49 ,  H01L2224/48091

Abstract: A semiconductor package structure includes a substrate, a semiconductor element, an encapsulant, an adhesion layer and a metal cap. The semiconductor element is disposed on the substrate. The encapsulant covers the semiconductor element. The adhesion layer is disposed on the encapsulant. The metal cap is attached to the encapsulant by the adhesion layer, and the metal cap is conformal with the encapsulant.