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公开(公告)号:US09443813B1
公开(公告)日:2016-09-13
申请号:US14639535
申请日:2015-03-05
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Yu-Hsiang Hsiao , Chiu-Wen Lee , Ping-Feng Yang , Kwang-Lung Lin
IPC: H01L23/00
CPC classification number: H01L24/13 , B23K1/0016 , B23K35/262 , B23K35/302 , B23K2101/40 , C22C9/02 , C22C13/00 , H01L24/05 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05022 , H01L2224/05147 , H01L2224/05572 , H01L2224/1182 , H01L2224/13025 , H01L2224/1308 , H01L2224/13083 , H01L2224/13084 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13565 , H01L2224/1357 , H01L2224/13582 , H01L2224/13611 , H01L2224/13644 , H01L2224/13647 , H01L2224/13655 , H01L2224/13664 , H01L2224/13686 , H01L2224/16146 , H01L2224/16503 , H01L2224/16507 , H01L2224/81193 , H01L2224/8181 , H01L2224/81815 , H01L2225/06513 , H01L2225/06544 , H01L2225/06565 , H01L2225/06582 , H01L2924/01029 , H01L2924/01327 , H01L2924/014 , H01L2924/181 , H01L2924/3512 , H01L2924/00012 , H01L2924/00014
Abstract: The present disclosure relates to a semiconductor device and a method for manufacturing the same. The semiconductor device includes a semiconductor die, a semiconductor element and a solder layer. The semiconductor die includes a copper pillar. The semiconductor element includes a surface finish layer, wherein the material of the surface finish layer is a combination of at least two of nickel, gold, and palladium. The solder layer is disposed between the copper pillar and the surface finish layer. The solder layer includes a first intermetallic compound (IMC) and a second IMC, wherein the first IMC includes a combination of at least two of copper, nickel and tin. The second IMC is a combination of gold and tin, a combination of palladium and tin, or both.
Abstract translation: 本公开涉及一种半导体器件及其制造方法。 半导体器件包括半导体管芯,半导体元件和焊料层。 半导体管芯包括铜柱。 半导体元件包括表面光洁度层,其中表面光洁度层的材料是镍,金和钯中的至少两种的组合。 焊料层设置在铜柱和表面光洁度层之间。 焊料层包括第一金属间化合物(IMC)和第二IMC,其中第一IMC包括铜,镍和锡中的至少两种的组合。 第二个IMC是金和锡的组合,钯和锡的组合,或两者兼而有之。
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公开(公告)号:US10217649B2
公开(公告)日:2019-02-26
申请号:US15619415
申请日:2017-06-09
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Jin-Yuan Lai , Tang-Yuan Chen , Ying-Xu Lu , Dao-Long Chen , Kwang-Lung Lin , Chih-Pin Hung , Tse-Chuan Chou , Ming-Hung Chen , Chi-Hung Pan
IPC: H01L23/49 , H01L21/56 , H01L23/00 , H01L21/48 , H01L23/498
Abstract: A semiconductor device package includes a substrate, a semiconductor device, and an underfill. The substrate includes a top surface defining a mounting area, and a barrier section on the top surface and adjacent to the mounting area. The semiconductor device is mounted on the mounting area of the substrate. The underfill is disposed between the semiconductor device and the mounting area and the barrier section of the substrate. A contact angle between a surface of the underfill and the barrier section is greater than or equal to about 90 degrees.
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公开(公告)号:US09953930B1
公开(公告)日:2018-04-24
申请号:US15299236
申请日:2016-10-20
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Ying-Ta Chiu , Chiu-Wen Lee , Dao-Long Chen , Po-Hsien Sung , Ping-Feng Yang , Kwang-Lung Lin
IPC: H01L21/00 , H01L23/10 , H01L23/552
CPC classification number: H01L23/60 , H01L21/56 , H01L21/565 , H01L23/06 , H01L23/10 , H01L23/3128 , H01L23/3135 , H01L23/49811 , H01L23/49827 , H01L23/552 , H01L24/49 , H01L2224/48091
Abstract: A semiconductor package structure includes a substrate, a semiconductor element, an encapsulant, an adhesion layer and a metal cap. The semiconductor element is disposed on the substrate. The encapsulant covers the semiconductor element. The adhesion layer is disposed on the encapsulant. The metal cap is attached to the encapsulant by the adhesion layer, and the metal cap is conformal with the encapsulant.
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公开(公告)号:US09960136B2
公开(公告)日:2018-05-01
申请号:US15239745
申请日:2016-08-17
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Yu-Hsiang Hsiao , Chiu-Wen Lee , Ping-Feng Yang , Kwang-Lung Lin
IPC: H01L23/00 , B23K1/00 , B23K35/26 , B23K35/30 , C22C9/02 , C22C13/00 , H01L25/065 , H01L25/00 , B23K101/40
CPC classification number: H01L24/13 , B23K1/0016 , B23K35/262 , B23K35/302 , B23K2101/40 , C22C9/02 , C22C13/00 , H01L24/05 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05022 , H01L2224/05147 , H01L2224/05572 , H01L2224/1182 , H01L2224/13025 , H01L2224/1308 , H01L2224/13083 , H01L2224/13084 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13565 , H01L2224/1357 , H01L2224/13582 , H01L2224/13611 , H01L2224/13644 , H01L2224/13647 , H01L2224/13655 , H01L2224/13664 , H01L2224/13686 , H01L2224/16146 , H01L2224/16503 , H01L2224/16507 , H01L2224/81193 , H01L2224/8181 , H01L2224/81815 , H01L2225/06513 , H01L2225/06544 , H01L2225/06565 , H01L2225/06582 , H01L2924/01029 , H01L2924/01327 , H01L2924/014 , H01L2924/181 , H01L2924/3512 , H01L2924/00012 , H01L2924/00014
Abstract: A semiconductor device includes a first circuit layer, a copper pillar disposed adjacent to the first circuit layer, a second circuit layer and a solder layer. The second circuit layer includes an electrical contact and a surface finish layer disposed on the electrical contact, wherein a material of the surface finish layer is a combination of at least two of nickel, gold, and palladium. The solder layer is disposed between the copper pillar and the surface finish layer. The solder layer includes a first intermetallic compound (IMC) and a second IMC, wherein the first IMC includes a combination of two or more of copper, nickel and tin, and the second IMC includes a combination of gold and tin, a combination of palladium and tin, or both.
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