公开(公告)号：US10181448B2

公开(公告)日：2019-01-15

申请号：US15076831

申请日：2016-03-22

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Pin Hung ,  Dao-Long Chen ,  Ying-Ta Chiu ,  Ping-Feng Yang

IPC: H01L23/00

Abstract: A semiconductor device includes a semiconductor element, a trace disposed adjacent to a surface of the semiconductor element, a bonding pad disposed adjacent to the surface of the semiconductor element and connected to the trace, and a pillar disposed on the bonding pad. The pillar includes a first end wall, a second end wall opposite the first end wall, a first side wall, and a second side wall opposite the first side wall. The first side wall and the second side wall connect the first end wall to the second end wall. One or both of the first side wall and the second side wall incline inwardly from the first end wall to the second end wall. The pillar is disposed on the bonding pad such that the first end wall is closer to the trace than is the second end wall.

公开(公告)号：US09960136B2

公开(公告)日：2018-05-01

申请号：US15239745

申请日：2016-08-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Hsiang Hsiao ,  Chiu-Wen Lee ,  Ping-Feng Yang ,  Kwang-Lung Lin

IPC: H01L23/00 ,  B23K1/00 ,  B23K35/26 ,  B23K35/30 ,  C22C9/02 ,  C22C13/00 ,  H01L25/065 ,  H01L25/00 ,  B23K101/40

CPC classification number: H01L24/13 ,  B23K1/0016 ,  B23K35/262 ,  B23K35/302 ,  B23K2101/40 ,  C22C9/02 ,  C22C13/00 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/1182 ,  H01L2224/13025 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/13686 ,  H01L2224/16146 ,  H01L2224/16503 ,  H01L2224/16507 ,  H01L2224/81193 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2225/06582 ,  H01L2924/01029 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor device includes a first circuit layer, a copper pillar disposed adjacent to the first circuit layer, a second circuit layer and a solder layer. The second circuit layer includes an electrical contact and a surface finish layer disposed on the electrical contact, wherein a material of the surface finish layer is a combination of at least two of nickel, gold, and palladium. The solder layer is disposed between the copper pillar and the surface finish layer. The solder layer includes a first intermetallic compound (IMC) and a second IMC, wherein the first IMC includes a combination of two or more of copper, nickel and tin, and the second IMC includes a combination of gold and tin, a combination of palladium and tin, or both.

公开(公告)号：US09741675B2

公开(公告)日：2017-08-22

申请号：US14599366

申请日：2015-01-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Dao-Long Chen ,  Ping-Feng Yang ,  Chang-Chi Lee ,  Chien-Fan Chen

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00

CPC classification number: H01L24/13 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/0614 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1161 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13007 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1414 ,  H01L2224/16055 ,  H01L2224/16056 ,  H01L2224/81191 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014

Abstract: The present disclosure relates to bump structures and a semiconductor device and semiconductor device package having the same. The semiconductor device includes a body, at least one conductive metal pad and at least one metal pillar. The body includes a first surface. The at least one conductive metal pad is disposed on the first surface. Each metal pillar is formed on a corresponding conductive metal pad. Each metal pillar has a concave side wall and a convex side wall opposite the first concave side wall, and the concave side wall and the convex side wall are orthogonal to the corresponding conductive metal pad.

公开(公告)号：US11075186B2

公开(公告)日：2021-07-27

申请号：US15429024

申请日：2017-02-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ian Hu ,  Jia-Rung Ho ,  Jin-Feng Yang ,  Chih-Pin Hung ,  Ping-Feng Yang

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/31 ,  H01L23/04 ,  H01L23/373

Abstract: A semiconductor package includes a substrate, a semiconductor chip and a heat dissipation structure. The semiconductor chip includes a first surface, a second surface opposite to the first surface, and at least one chip pad disposed adjacent to the first surface. The chip pad is electrically connected to the substrate. The heat dissipation structure is disposed adjacent to the second surface of the semiconductor chip and a portion of the substrate. An area of the heat dissipation structure is greater than an area of the semiconductor chip.

公开(公告)号：US09953930B1

公开(公告)日：2018-04-24

申请号：US15299236

申请日：2016-10-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ying-Ta Chiu ,  Chiu-Wen Lee ,  Dao-Long Chen ,  Po-Hsien Sung ,  Ping-Feng Yang ,  Kwang-Lung Lin

IPC: H01L21/00 ,  H01L23/10 ,  H01L23/552

CPC classification number: H01L23/60 ,  H01L21/56 ,  H01L21/565 ,  H01L23/06 ,  H01L23/10 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/49 ,  H01L2224/48091

Abstract: A semiconductor package structure includes a substrate, a semiconductor element, an encapsulant, an adhesion layer and a metal cap. The semiconductor element is disposed on the substrate. The encapsulant covers the semiconductor element. The adhesion layer is disposed on the encapsulant. The metal cap is attached to the encapsulant by the adhesion layer, and the metal cap is conformal with the encapsulant.

公开(公告)号：US10818517B2

公开(公告)日：2020-10-27

申请号：US16285002

申请日：2019-02-25

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Huang Han Chen ,  Ping-Feng Yang

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/78

Abstract: A method for manufacturing a semiconductor package structure includes providing a semiconductor chip, encapsulating the semiconductor chip via a package body, the package body having a first surface opposite to a second surface, and coating a first self-assembled monolayer (SAM) over the first surface and the second surface of the package body.

公开(公告)号：US10658319B2

公开(公告)日：2020-05-19

申请号：US16247437

申请日：2019-01-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Pin Hung ,  Dao-Long Chen ,  Ying-Ta Chiu ,  Ping-Feng Yang

IPC: H01L23/00

Abstract: A semiconductor device includes a semiconductor element, a trace disposed adjacent to a surface of the semiconductor element, a bonding pad disposed adjacent to the surface of the semiconductor element and connected to the trace, and a pillar disposed on the bonding pad. The pillar includes a first end wall, a second end wall opposite the first end wall, a first side wall, and a second side wall opposite the first side wall. The first side wall and the second side wall connect the first end wall to the second end wall. One or both of the first side wall and the second side wall incline inwardly from the first end wall to the second end wall. The pillar is disposed on the bonding pad such that the first end wall is closer to the trace than is the second end wall.

公开(公告)号：US09443813B1

公开(公告)日：2016-09-13

申请号：US14639535

申请日：2015-03-05

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Hsiang Hsiao ,  Chiu-Wen Lee ,  Ping-Feng Yang ,  Kwang-Lung Lin

IPC: H01L23/00

CPC classification number: H01L24/13 ,  B23K1/0016 ,  B23K35/262 ,  B23K35/302 ,  B23K2101/40 ,  C22C9/02 ,  C22C13/00 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/1182 ,  H01L2224/13025 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/13686 ,  H01L2224/16146 ,  H01L2224/16503 ,  H01L2224/16507 ,  H01L2224/81193 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2225/06582 ,  H01L2924/01029 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: The present disclosure relates to a semiconductor device and a method for manufacturing the same. The semiconductor device includes a semiconductor die, a semiconductor element and a solder layer. The semiconductor die includes a copper pillar. The semiconductor element includes a surface finish layer, wherein the material of the surface finish layer is a combination of at least two of nickel, gold, and palladium. The solder layer is disposed between the copper pillar and the surface finish layer. The solder layer includes a first intermetallic compound (IMC) and a second IMC, wherein the first IMC includes a combination of at least two of copper, nickel and tin. The second IMC is a combination of gold and tin, a combination of palladium and tin, or both.

Abstract translation: 本公开涉及一种半导体器件及其制造方法。 半导体器件包括半导体管芯，半导体元件和焊料层。 半导体管芯包括铜柱。 半导体元件包括表面光洁度层，其中表面光洁度层的材料是镍，金和钯中的至少两种的组合。 焊料层设置在铜柱和表面光洁度层之间。 焊料层包括第一金属间化合物（IMC）和第二IMC，其中第一IMC包括铜，镍和锡中的至少两种的组合。 第二个IMC是金和锡的组合，钯和锡的组合，或两者兼而有之。