公开(公告)号：US20240096819A1

公开(公告)日：2024-03-21

申请号：US18241531

申请日：2023-09-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bong Ken YU

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/562 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49833 ,  H01L25/18 ,  H10B80/00 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/16227

Abstract: There is provided a semiconductor package in which warpage of an interposer is prevented to improve product reliability. The semiconductor package comprising a first substrate including a first insulating layer, and a first conductive pattern disposed in the first insulating layer, a semiconductor chip disposed on the first substrate, an interposer disposed on the semiconductor chip, wherein the interposer includes a second insulating layer, and a second conductive pattern disposed in the second insulating layer, a support member disposed on a bottom surface of the second insulating layer and is in contact with an upper surface of the semiconductor chip, wherein the support member includes a first lower pad and a bump disposed under the first lower pad and a first connection member disposed between the first substrate and the interposer so as to connect the first conductive pattern and the second conductive pattern to each other.

公开(公告)号：US20240088079A1

公开(公告)日：2024-03-14

申请号：US18456905

申请日：2023-08-28

Applicant: DUKSAN HI METAL CO., LTD.

Inventor： Eun Dong Jin ,  LEE HYUNKYU ,  Kim Kyung Tae ,  Bae Sung Moon ,  Park Eun Kwang ,  Seong Taek Kim ,  Kim Jin-Gyu ,  CHU YONGCHEOL ,  OH HEEBONG

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L24/13 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/1111 ,  H01L2224/1112 ,  H01L2224/13005 ,  H01L2224/13111 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13149 ,  H01L2224/13155 ,  H01L2224/1316 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13618 ,  H01L2224/13623 ,  H01L2224/13624 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13663 ,  H01L2224/16225 ,  H01L2924/01005 ,  H01L2924/0132 ,  H01L2924/014

Abstract: An aspect of the present invention provides a metal pillar in a columnar shape formed by cutting a metal wire to a predetermined length. The metal pillar has a burr length of 0.1 to 0.5 μm on the cutting surface, an electrical conductivity of 11 to 101% IACS, and a Vickers hardness of 150 to 300 HV.

公开(公告)号：US11923326B2

公开(公告)日：2024-03-05

申请号：US17875291

申请日：2022-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ching-Yu Chang ,  Ming-Da Cheng ,  Ming-Hui Weng

IPC: H01L23/00 ,  C08G73/10

CPC classification number: H01L24/05 ,  C08G73/1078 ,  C08G73/1085 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02251 ,  H01L2224/0226 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05176 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13123 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13149 ,  H01L2224/13155 ,  H01L2224/1316 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13179 ,  H01L2224/1318 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/07025

Abstract: A method of manufacturing a bump structure includes forming a passivation layer over a substrate. A metal pad structure is formed over the substrate, wherein the passivation layer surrounds the metal pad structure. A polyimide layer including a polyimide is formed over the passivation layer and the metal pad structure. A metal bump is formed over the metal pad structure and the polyimide layer. The polyimide is a reaction product of a dianhydride and a diamine, wherein at least one of the dianhydride and the diamine comprises one selected from the group consisting of a cycloalkane, a fused ring, a bicycloalkane, a tricycloalkane, a bicycloalkene, a tricycloalkene, a spiroalkane, and a heterocyclic ring.

公开(公告)号：US20230223324A1

公开(公告)日：2023-07-13

申请号：US18151250

申请日：2023-01-06

Applicant: Regents of the University of Minnesota

Inventor： Bethanie J Stadler ,  Rhonda R. Franklin

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01R12/52 ,  H05K1/18 ,  H05K1/14 ,  H05K3/36 ,  H05K3/34 ,  H05K3/00 ,  H05K3/42

CPC classification number: H01L23/49827 ,  H01L23/5384 ,  H01L24/16 ,  H01L24/81 ,  H01L21/486 ,  H01L24/13 ,  H01R12/52 ,  H05K1/181 ,  H05K1/145 ,  H05K3/368 ,  H05K3/3436 ,  H05K3/3494 ,  H05K3/0014 ,  H05K3/424 ,  H01L2224/16235 ,  H01L2224/81222 ,  H01L2224/81815 ,  H01L2224/13111 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13138 ,  H01L2224/13109 ,  H01L2924/01014 ,  H05K2201/10378 ,  H01L2224/81192 ,  H05K2203/0723

Abstract: A device includes a porous substrate that include a plurality of pores and a plurality of nanodevices dispersed in at least a portion of the plurality of pores. Each of the plurality of nanodevices includes a magnetic nanowire and a solder nanoparticle. The magnetic nanowires are configured to generate heat in response to an alternating magnetic field. The solder nanoparticles are configured to receive a portion of the heat and reflow to connect to one or more devices or surfaces.

公开(公告)号：US20230215791A1

公开(公告)日：2023-07-06

申请号：US17933272

申请日：2022-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinmo Kwon

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/16 ,  H01L23/49838 ,  H01L2224/48227 ,  H01L2224/16227 ,  H01L2224/45144 ,  H01L2224/45139 ,  H01L2224/45116 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L24/45 ,  H01L2224/32225 ,  H01L24/32 ,  H01L2224/05647 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05616 ,  H01L2224/05666 ,  H01L24/05 ,  H01L2224/13111 ,  H01L2224/13109 ,  H01L2224/13113 ,  H01L2224/1312 ,  H01L2224/13147 ,  H01L2224/13139 ,  H01L2224/13118 ,  H01L2224/13116 ,  H01L24/13 ,  H01L2224/85411 ,  H01L2224/85416 ,  H01L2224/85455 ,  H01L2224/85444 ,  H01L24/85 ,  H01L2224/81411 ,  H01L2224/81416 ,  H01L2224/81455 ,  H01L2224/81444 ,  H01L24/81 ,  H01L2224/73265 ,  H01L24/73

Abstract: A semiconductor package includes: a substrate including an insulating layer, a plurality of pads on the insulating layer, a surface protective layer covering the insulating layer and having first through-holes exposing at least a portion of the insulating layer and second through-holes exposing at least a portion of each of the plurality of pads, a plurality of first dummy patterns extending from the plurality of pads to the first through-holes, and a plurality of second dummy patterns extending from the first through-holes to an edge of the insulating layer; a semiconductor chip on the substrate and including connection terminals electrically connected to the plurality of pads exposed through the second through-holes; and an encapsulant encapsulating at least a portion of the semiconductor chip and filling the first through-holes, wherein a separation distance between the first through-holes is greater than a separation distance between the second through-holes.

公开(公告)号：US20230145304A1

公开(公告)日：2023-05-11

申请号：US17749016

申请日：2022-05-19

Applicant: InnoLux Corporation

Inventor： Yi-Hung LIN ,  Chun-Hung LAI ,  Chun-Chin FAN

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L23/49822 ,  H01L24/13 ,  H01L21/4857 ,  H01L21/4853 ,  H01L2224/13021 ,  H01L2224/13144 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13176 ,  H01L2224/13124 ,  H01L2224/13157 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/1318 ,  H01L2224/13149 ,  H01L2224/13118 ,  H01L2224/13578 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/1369 ,  H01L24/16 ,  H01L2224/16238 ,  H01L2224/1182 ,  H01L24/11 ,  H01L2221/68345 ,  H01L21/6835

Abstract: An electronic device and a method for manufacturing the same are provided. The electronic device includes: a first insulating layer; a first metal bump disposed on the first insulating layer; and a second insulating layer disposed on the first metal bump, wherein the second insulating layer includes a first opening exposing a portion of the first metal bump, wherein a thickness of the first insulating layer is greater than a thickness of the second insulating layer.

公开(公告)号：US20190206841A1

公开(公告)日：2019-07-04

申请号：US16106521

申请日：2018-08-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Lyong KIM ,  Seung Duk BAEK

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/5383 ,  H01L24/05 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05169 ,  H01L2224/05184 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2224/13007 ,  H01L2224/13017 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/013 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01029 ,  H01L2924/01083 ,  H01L2924/0103 ,  H01L2924/01074 ,  H01L2924/01023 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/81

Abstract: A semiconductor package includes a first semiconductor chip having a first chip substrate, the first chip substrate having a first upper surface and a first lower surface opposite to each other, a first through-silicon via (TSV), a lower connection pad and a first lower passivation layer on the first lower surface of the first chip substrate, the first lower passivation layer exposing a portion of the lower connection pad, an upper connection pad and a first upper passivation layer on the first upper surface of the first chip substrate, the first upper passivation layer including a first upper inorganic material layer, and a second semiconductor chip connected to the first semiconductor chip, the second semiconductor chip including a second TSV, wherein the first lower passivation layer has a stacked structure of a first lower inorganic material layer and a lower organic material layer.

公开(公告)号：US10062657B2

公开(公告)日：2018-08-28

申请号：US15518219

申请日：2015-10-09

Applicant: ISHIHARA CHEMICAL CO., LTD.

Inventor： Shoya Iuchi ,  Masaru Hatabe

IPC: H01L23/00 ,  H05K3/34

CPC classification number: H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11848 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/13139 ,  H05K3/34 ,  H01L2924/014 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01083 ,  H01L2924/01047

Abstract: In order to manufacture an alloy bump, a resist pattern having openings which expose a substrate is formed on the substrate, an under-bump metal is formed on the substrate inside the openings, a first plating film is formed on the under-bump metal by electroplating, a second plating film containing no metal components which are contained in the first plating film is formed on the first plating film by electroplating, the resist pattern is removed, and the alloy bump is formed by heat treating the substrate to thereby alloy the first plating film and the second plating film.

公开(公告)号：US09881890B2

公开(公告)日：2018-01-30

申请号：US15284714

申请日：2016-10-04

Applicant: OLYMPUS CORPORATION

Inventor： Kazuaki Kojima

IPC: H01L23/00 ,  H05K3/36 ,  H05K3/46 ,  H01L21/48 ,  H01L23/498 ,  H01L27/146

CPC classification number: H01L24/16 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/4985 ,  H01L23/49894 ,  H01L24/75 ,  H01L24/81 ,  H01L27/14636 ,  H01L2224/13111 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16238 ,  H01L2224/50 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2924/014 ,  H01L2924/12043 ,  H05K3/363 ,  H05K3/4691 ,  H05K2201/068

Abstract: A semiconductor module includes an image pickup device on which a bump is disposed, and a flexible wiring board having a flexible resin as a base and including a wire having a bonding electrode at a distal end portion solder-bonded to the bump, in which the bonding electrode is pressed against the bump by bending/deformation of the wiring board caused by application of heat to a solder bonding temperature.

公开(公告)号：US09881859B2

公开(公告)日：2018-01-30

申请号：US14273882

申请日：2014-05-09

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Dong Wook Kim ,  Jae Sik Lee ,  Shiqun Gu ,  Ratibor Radojcic

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/522 ,  H01L21/78 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L23/528 ,  H01L21/311 ,  H05K1/09 ,  H05K1/11 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L21/31127 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16235 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81466 ,  H01L2224/81484 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/20648 ,  H01L2924/3511 ,  H05K1/09 ,  H05K1/115 ,  H05K2201/09563 ,  H01L2924/014 ,  H01L2224/81

Abstract: A substrate block is provided that has an increased width. The substrate block comprises two substrate bars, and the substrate bars each comprise a substrate and a plurality of filled vias through the substrate. The substrate block may be used to manufacture package substrates, and these package substrate may be incorporated into a PoP structure. The package substrate includes a carrier having a plurality of vertical interconnections and a bar coupled to the vertical interconnections.