公开(公告)号：US09768103B2

公开(公告)日：2017-09-19

申请号：US14990425

申请日：2016-01-07

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Hui Wang ,  Ying-Te Ou

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H05K1/18 ,  H05K3/42 ,  H05K3/46

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/185 ,  H05K1/188 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09536 ,  H05K2201/10674 ,  H05K2203/063 ,  Y10T29/4913 ,  Y10T29/49204 ,  Y10T29/49213

Abstract: An embedded chip substrate includes a first insulation layer, a core layer, a chip, a second insulation layer, a first circuit layer, and a second circuit layer. The core layer disposed on the first insulation layer has an opening that exposes a portion of the first insulation layer. The chip is adhered into a recess constructed by the opening and the first insulation layer. The second insulation layer is disposed on the core layer for covering the chip. The first circuit layer is disposed at the outer side of the first insulation layer located between the first circuit layer and the core layer. The second circuit layer is disposed at the outer side of the second insulation layer located between the second circuit layer and the core layer. The first circuit layer is electrically connected to the second circuit layer that is electrically connected to the chip.

公开(公告)号：US08987734B2

公开(公告)日：2015-03-24

申请号：US13843304

申请日：2013-03-15

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Hui Wang

IPC: H01L23/58 ,  H01L21/66 ,  H01L27/04 ,  H01L23/00

CPC classification number: H01L22/14 ,  H01L22/34 ,  H01L24/73 ,  H01L27/04 ,  H01L2224/48465 ,  H01L2924/181 ,  H01L2924/00

Abstract: The present invention provides a semiconductor wafer, semiconductor package and semiconductor process. The semiconductor wafer includes a substrate, at least one metal segment and a plurality of dielectric layers. The semiconductor wafer is defined as a plurality of die areas and a plurality of trench areas, each of the die areas has an integrated circuit including a plurality of patterned metal layers disposed between the dielectric layers. The trench areas are disposed between the die areas, and the at least one metal segment is disposed in the trench area and insulated from the integrated circuit of the die area.

Abstract translation: 本发明提供半导体晶片，半导体封装和半导体工艺。 半导体晶片包括衬底，至少一个金属段和多个电介质层。 半导体晶片被定义为多个管芯区域和多个沟槽区域，每个管芯区域都具有集成电路，该集成电路包括设置在电介质层之间的多个图案化金属层。 沟槽区域设置在管芯区域之间，并且至少一个金属段设置在沟槽区域中并与管芯区域的集成电路绝缘。

公开(公告)号：US20140264716A1

公开(公告)日：2014-09-18

申请号：US13843304

申请日：2013-03-15

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Yung-Hui Wang

IPC: H01L21/66 ,  H01L27/04

CPC classification number: H01L22/14 ,  H01L22/34 ,  H01L24/73 ,  H01L27/04 ,  H01L2224/48465 ,  H01L2924/181 ,  H01L2924/00

Abstract: The present invention provides a semiconductor wafer, semiconductor package and semiconductor process. The semiconductor wafer includes a substrate, at least one metal segment and a plurality of dielectric layers. The semiconductor wafer is defined as a plurality of die areas and a plurality of trench areas, each of the die areas has an integrated circuit including a plurality of patterned metal layers disposed between the dielectric layers. The trench areas are disposed between the die areas, and the at least one metal segment is disposed in the trench area and insulated from the integrated circuit of the die area.

Abstract translation: 本发明提供半导体晶片，半导体封装和半导体工艺。 半导体晶片包括衬底，至少一个金属段和多个电介质层。 半导体晶片被定义为多个管芯区域和多个沟槽区域，每个管芯区域都具有集成电路，该集成电路包括设置在电介质层之间的多个图案化金属层。 沟槽区域设置在管芯区域之间，并且至少一个金属段设置在沟槽区域中并与管芯区域的集成电路绝缘。

公开(公告)号：US11774673B2

公开(公告)日：2023-10-03

申请号：US17719277

申请日：2022-04-12

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Hsuan Wu ,  Yung-Hui Wang

IPC: G02B6/12 ,  G02B6/42

CPC classification number: G02B6/12 ,  G02B6/4204 ,  G02B2006/12061

Abstract: An optical communication package structure includes a wiring structure, at least one via structure, a redistribution structure, at least one optical device and at least one electrical device. The wiring structure includes a main portion and a conductive structure disposed on an upper surface of the main portion. The main portion defines at least one through hole extending through the main portion. The via structure is disposed in the at least one through hole of the main portion and electrically connected to the conductive structure. The redistribution structure is disposed on a lower surface of the main portion and electrically connected to the via structure. The optical device is disposed adjacent to the upper surface of the main portion and electrically connected to the conductive structure. The electrical device is disposed on and electrically connected to the conductive structure.

公开(公告)号：US11300727B2

公开(公告)日：2022-04-12

申请号：US16528331

申请日：2019-07-31

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Hsuan Wu ,  Yung-Hui Wang

IPC: G02B6/12 ,  G02B6/42

Abstract: An optical communication package structure includes a wiring structure, at least one via structure, a redistribution structure, at least one optical device and at least one electrical device. The wiring structure includes a main portion and a conductive structure disposed on an upper surface of the main portion. The main portion defines at least one through hole extending through the main portion. The via structure is disposed in the at least one through hole of the main portion and electrically connected to the conductive structure. The redistribution structure is disposed on a lower surface of the main portion and electrically connected to the via structure. The optical device is disposed adjacent to the upper surface of the main portion and electrically connected to the conductive structure. The electrical device is disposed on and electrically connected to the conductive structure.