公开(公告)号：US11430761B2

公开(公告)日：2022-08-30

申请号：US16793991

申请日：2020-02-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yun-Ching Hung ,  Yung-Sheng Lin ,  Chin-Li Kao

IPC: H01L23/00

Abstract: Present disclosure provides a semiconductor package, including a first substrate having a first active surface and a first trench recessed from the first active surface, a second substrate having a second trench facing the first trench, and a pathway cavity defined by the first trench and the second trench. The first trench comprises a first metal protrusion and a first insulating protrusion. A method for manufacturing the semiconductor package described herein is also disclosed.

公开(公告)号：US11798907B2

公开(公告)日：2023-10-24

申请号：US17092195

申请日：2020-11-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Sheng Lin ,  Yun-Ching Hung ,  An-Hsuan Hsu ,  Chung-Hung Lai

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/10145 ,  H01L2224/1357 ,  H01L2224/13541 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/8102 ,  H01L2224/81007 ,  H01L2224/81193 ,  H01L2224/81232

Abstract: A semiconductor package includes a first substrate, a first flow channel and a second flow channel. The first flow channel is on the first substrate. The second flow channel is on the first substrate and in fluid communication with the first flow channel. The second flow channel is spaced from an inlet and an outlet of the first flow channel. The first flow channel and the second flow channel constitute a bonding region of the first substrate.

公开(公告)号：US11257776B2

公开(公告)日：2022-02-22

申请号：US16573672

申请日：2019-09-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Sheng Lin ,  Chin-Li Kao ,  Hsu-Nan Fang

IPC: H01L25/065 ,  H01L25/16 ,  H01L25/00 ,  H01L25/18 ,  H01L23/00

Abstract: A semiconductor package structure includes a semiconductor die surface having a narrower pitch region and a wider pitch region adjacent to the narrower pitch region, a plurality of first type conductive pillars in the narrower pitch region, each of the first type conductive pillars having a copper-copper interface, and a plurality of second type conductive pillars in the wider pitch region, each of the second type conductive pillars having a copper-solder interface. A method for manufacturing the semiconductor package structure described herein is also disclosed.

公开(公告)号：US12057670B2

公开(公告)日：2024-08-06

申请号：US17219613

申请日：2021-03-31

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： An-Hsuan Hsu ,  Yung-Sheng Lin

IPC: H01R4/62 ,  H01R12/52 ,  H01R12/57 ,  H01R43/02 ,  H05K3/36 ,  H05K3/10

CPC classification number: H01R4/625 ,  H01R12/52 ,  H01R12/57 ,  H01R43/02 ,  H05K3/368 ,  H05K3/108 ,  H05K2203/0723

Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first substrate, a second substrate, and a solid solution layer. The first substrate includes a first metal layer, and the first metal layer includes a first metal. The second substrate includes a second metal layer. The solid solution layer electrically connects the first metal layer to the second metal layer. The solid solution layer includes a first metal-rich layer.