High performance PMOSFET using split-polysilicon CMOS process
incorporating advanced stacked capacitior cells for fabricating
multi-megabit DRAMS
    1.
    发明授权
    High performance PMOSFET using split-polysilicon CMOS process incorporating advanced stacked capacitior cells for fabricating multi-megabit DRAMS 失效
    采用分裂多晶硅CMOS工艺的高性能PMOSFET,包含用于制造多兆位DRAMS的先进的堆叠电容单元

    公开(公告)号:US5716862A

    公开(公告)日:1998-02-10

    申请号:US491179

    申请日:1995-06-16

    CPC分类号: H01L21/28061 H01L21/28247

    摘要: This invention is a process for manufacturing dynamic random access memories using stacked container capacitor cells in a split-polysilicon CMOS manufacturing flow. The split-polysilicon flow denotes that N-channel and P-channel transistor gates are formed from a single conductive layer (typically a doped polysilicon layer) using separate masking steps. In one embodiment of the present invention teaches a semiconductor manufacturing process for forming p-channel devices by the steps of: defining p-channel transistor gate electrodes having substantially vertical sidewalls over n-well regions; performing a p-type impurity implant into the n-well regions to form p-channel source and drain terminals on opposing sides of each the p-channel transistor gate electrodes; performing an angled n-type impurity implant into the n-well regions to form an n-type halo around the p-channel source and drain terminals; performing a low temperature oxidation step at a temperature ranging between 600.degree.-957.degree. C., to form poly gate sidewall oxidation about the vertical sidewalls of the p-channel transistor gate electrodes; and performing a p-type impurity implant into the n-well regions.

    摘要翻译: 本发明是使用分裂多晶硅CMOS制造流程中的堆叠容器电容器单元制造动态随机存取存储器的方法。 分离多晶硅流程表示使用单独的掩蔽步骤由单个导电层(通常为掺杂多晶硅层)形成N沟道和P沟道晶体管栅极。 在本发明的一个实施例中,教导了通过以下步骤形成p沟道器件的半导体制造工艺:定义在n-阱区上具有基本上垂直的侧壁的p沟道晶体管栅电极; 对n阱区域进行p型杂质注入,以在每个p沟道晶体管栅电极的相对侧上形成p沟道源极和漏极端子; 在n阱区域中执行倾斜的n型杂质注入以在p沟道源极和漏极端子周围形成n型光晕; 在600〜957℃的温度范围内进行低温氧化步骤,以形成围绕p沟道晶体管栅极垂直侧壁的多晶硅侧壁氧化; 以及对n阱区进行p型杂质注入。

    Method to form a DRAM capacitor using low temperature reoxidation
    2.
    发明授权
    Method to form a DRAM capacitor using low temperature reoxidation 失效
    使用低温再氧化形成DRAM电容器的方法

    公开(公告)号:US06787482B2

    公开(公告)日:2004-09-07

    申请号:US10223004

    申请日:2002-08-14

    IPC分类号: H01L2131

    摘要: An embodiment of the present invention teaches a capacitor dielectric in a wafer cluster tool for semiconductor device fabrication formed by a method by the steps of: forming nitride adjacent a layer by rapid thermal nitridation; and subjecting the nitride to an ozone ambient, wherein the ozone ambient is selected from the group consisting of an ambient containing an ultraviolet/ozone mixture, an ambient containing an ozone or an ambient containing an NF3/ozone mixture.

    摘要翻译: 本发明的实施例教导了用于半导体器件制造的晶片簇工具中的电容器电介质,该方法通过以下步骤形成:通过快速热氮化形成邻近层的氮化物; 以及使所述氮化物经受臭氧环境,其中所述臭氧环境选自含有紫外线/臭氧混合物的环境,含有臭氧的环境或含有NF 3 /臭氧混合物的环境。

    Method to form a DRAM capacitor using low temperature reoxidation
    3.
    发明授权
    Method to form a DRAM capacitor using low temperature reoxidation 失效
    使用低温再氧化形成DRAM电容器的方法

    公开(公告)号:US06162666A

    公开(公告)日:2000-12-19

    申请号:US368481

    申请日:1999-08-04

    摘要: An embodiment of the present invention teaches a capacitor dielectric in a wafer cluster tool for semiconductor device fabrication formed by a method by the steps of: forming nitride adjacent a layer by rapid thermal nitridation; and subjecting the nitride to an ozone ambient, wherein the ozone ambient is selected from the group consisting of an ambient containing an the presence of ultraviolet light and ozone gas, an ambient containing an ozone gas or an ambient containing an NF.sub.3 /ozone gas mixture.

    摘要翻译: 本发明的实施例教导了用于半导体器件制造的晶片簇工具中的电容器电介质,该方法通过以下步骤形成:通过快速热氮化形成邻近层的氮化物; 以及使所述氮化物经受臭氧环境,其中所述臭氧环境选自包含存在紫外线和臭氧气体的环境,含有臭氧气体的环境或含有NF 3 /臭氧气体混合物的环境。

    Method to form a DRAM capacitor using low temperature reoxidation
    4.
    发明授权
    Method to form a DRAM capacitor using low temperature reoxidation 有权
    使用低温再氧化形成DRAM电容器的方法

    公开(公告)号:US06448133B1

    公开(公告)日:2002-09-10

    申请号:US09717941

    申请日:2000-11-20

    IPC分类号: H01L218242

    摘要: An embodiment of the present invention teaches a capacitor dielectric in a wafer cluster tool for semiconductor device fabrication formed by a method by the steps of: forming nitride adjacent a layer by rapid thermal nitridation; and subjecting the nitride to an ozone ambient, wherein the ozone ambient is selected from the group consisting of an ambient containing an the presence of ultraviolet light and ozone gas, an ambient containing ozone gas or an ambient containing an NF3/ozone gas mixture.

    摘要翻译: 本发明的实施例教导了用于半导体器件制造的晶片簇工具中的电容器电介质,该方法通过以下步骤形成:通过快速热氮化形成邻近层的氮化物; 并且对所述氮化物进行臭氧环境处理,其中所述臭氧环境选自包含存在紫外线和臭氧气体的环境,含有臭氧气体的环境或含有NF 3 /臭氧气体混合物的环境。

    Method to form a DRAM capacitor using low temperature reoxidation
    5.
    发明授权
    Method to form a DRAM capacitor using low temperature reoxidation 失效
    使用低温再氧化形成DRAM电容器的方法

    公开(公告)号:US5966595A

    公开(公告)日:1999-10-12

    申请号:US968382

    申请日:1997-11-12

    摘要: An embodiment of the present invention teaches a capacitor dielectric in a wafer cluster tool for semiconductor device fabrication formed by a method by the steps of: forming nitride adjacent a layer by rapid thermal nitridation; and subjecting the nitride to an ozone ambient, wherein the ozone ambient is selected from the group consisting of an ambient containing the presence of ultraviolet light and ozone gas, an ambient containing ozone gas or an ambient containing an NF.sub.3 /ozone gas mixture.

    摘要翻译: 本发明的实施例教导了用于半导体器件制造的晶片簇工具中的电容器电介质,该方法通过以下步骤形成:通过快速热氮化形成邻近层的氮化物; 并且使氮化物经受臭氧环境,其中臭氧环境选自包含紫外线和臭氧气体的环境,含有臭氧气体的环境或含有NF 3 /臭氧气体混合物的环境。

    Method of preventing null formation in phase shifted photomasks
    6.
    发明授权
    Method of preventing null formation in phase shifted photomasks 失效
    防止相移光掩模中无效形成的方法

    公开(公告)号:US5281500A

    公开(公告)日:1994-01-25

    申请号:US754893

    申请日:1991-09-04

    IPC分类号: G03F1/30 H01L21/027 G03F9/00

    CPC分类号: G03F1/30

    摘要: A method of preventing null formation is performed on a phase shifted photomask including a clear quartz substrate, dark chrome feature features, and alternating clear phase shifters raised from the substrate. The phase shifter features are terminated in a transmissive, optically clear edge. To prevent null formation and consequent formation of stringers on the surface of the integrated circuit, the substantially vertical edge of the optically clear end of the phase shifter is tapered. The slope at any point along the tapered edge between the photomask substrate and the phase shifter is set to an angle, typically less than forty-five degrees, shallow enough that the point spread function does not produce an image. The point spread function of the imaging system spreads out the null, which is therefore not printed into the photoresist layer on the integrated circuit. The tapered edge of the phase shifter is created by either discrete or continuous etching methods. Both methods create the phase shifter and tapered edges simultaneously and are compatible with photomasks having either additive or subtractive type phase shifters.

    摘要翻译: 对包括透明石英基板,黑铬特征特征的相移光掩模以及从基板凸起的交替的透明移相器执行防止空白形成的方法。 移相器的特征端接在透射光学透明的边缘。 为了防止在集成电路的表面上的空隙形成和随之形成桁条,移相器的光学透明端的基本上垂直的边缘是锥形的。 沿着光掩模基板和移相器之间的锥形边缘的任何点处的斜率被设定为通常小于四十五度的角度,足以使点扩散函数不产生图像。 成像系统的点扩散功能扩展为零,因此不会印刷到集成电路上的光致抗蚀剂层中。 移相器的锥形边缘通过离散或连续蚀刻方法产生。 两种方法同时产生移相器和锥形边缘,并且与具有加法或减法型移相器的光掩模兼容。