利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

243 条记录 (耗时 0.024 秒)

    High performance PMOSFET using split-polysilicon CMOS process incorporating advanced stacked capacitior cells for fabricating multi-megabit DRAMS
    1.
    发明授权
    High performance PMOSFET using split-polysilicon CMOS process incorporating advanced stacked capacitior cells for fabricating multi-megabit DRAMS 失效
    采用分裂多晶硅CMOS工艺的高性能PMOSFET，包含用于制造多兆位DRAMS的先进的堆叠电容单元

    公开(公告)号：US5716862A

    公开(公告)日：1998-02-10

    申请号：US491179

    申请日：1995-06-16

    申请人： Aftab Ahmad ,  Randhir P. S. Thakur ,  Kirk Prall ,  Tyler Lowrey ,  Brett Rolfson

    发明人： Aftab Ahmad ,  Randhir P. S. Thakur ,  Kirk Prall ,  Tyler Lowrey ,  Brett Rolfson

    IPC分类号： H01L21/28 ,  H01L21/265 ,  H01L21/02 ,  H01L21/70 ,  H01L27/00

    CPC分类号： H01L21/28061 ,  H01L21/28247

    摘要： This invention is a process for manufacturing dynamic random access memories using stacked container capacitor cells in a split-polysilicon CMOS manufacturing flow. The split-polysilicon flow denotes that N-channel and P-channel transistor gates are formed from a single conductive layer (typically a doped polysilicon layer) using separate masking steps. In one embodiment of the present invention teaches a semiconductor manufacturing process for forming p-channel devices by the steps of: defining p-channel transistor gate electrodes having substantially vertical sidewalls over n-well regions; performing a p-type impurity implant into the n-well regions to form p-channel source and drain terminals on opposing sides of each the p-channel transistor gate electrodes; performing an angled n-type impurity implant into the n-well regions to form an n-type halo around the p-channel source and drain terminals; performing a low temperature oxidation step at a temperature ranging between 600.degree.-957.degree. C., to form poly gate sidewall oxidation about the vertical sidewalls of the p-channel transistor gate electrodes; and performing a p-type impurity implant into the n-well regions.

    摘要翻译： 本发明是使用分裂多晶硅CMOS制造流程中的堆叠容器电容器单元制造动态随机存取存储器的方法。 分离多晶硅流程表示使用单独的掩蔽步骤由单个导电层（通常为掺杂多晶硅层）形成N沟道和P沟道晶体管栅极。 在本发明的一个实施例中，教导了通过以下步骤形成p沟道器件的半导体制造工艺：定义在n-阱区上具有基本上垂直的侧壁的p沟道晶体管栅电极; 对n阱区域进行p型杂质注入，以在每个p沟道晶体管栅电极的相对侧上形成p沟道源极和漏极端子; 在n阱区域中执行倾斜的n型杂质注入以在p沟道源极和漏极端子周围形成n型光晕; 在600〜957℃的温度范围内进行低温氧化步骤，以形成围绕p沟道晶体管栅极垂直侧壁的多晶硅侧壁氧化; 以及对n阱区进行p型杂质注入。

    Method of forming a resistor and integrated circuitry having a resistor construction
    3.
    发明授权
    Method of forming a resistor and integrated circuitry having a resistor construction 有权
    形成电阻器的方法和具有电阻器结构的集成电路

    公开(公告)号：US06130137A

    公开(公告)日：2000-10-10

    申请号：US170792

    申请日：1998-10-13

    申请人： Kirk Prall ,  Pierre C. Fazan ,  Aftab Ahmad ,  Howard E. Rhodes ,  Werner Juengling ,  Pai-Hung Pan ,  Tyler Lowrey

    发明人： Kirk Prall ,  Pierre C. Fazan ,  Aftab Ahmad ,  Howard E. Rhodes ,  Werner Juengling ,  Pai-Hung Pan ,  Tyler Lowrey

    IPC分类号： H01L21/02 ,  H01L21/20

    CPC分类号： H01L28/20

    摘要： A method of forming a resistor from semiconductive material includes, a) providing a substrate; b) providing a layer of semiconductive material over the substrate; c) providing a pair of openings into the semiconductive material layer; d) plugging the pair of openings with an electrically conductive material to define a pair of electrically conductive pillars within the semiconductive material, the pair of pillars having semiconductive material extending therebetween to provide a resistor construction; and e) providing a conductive node to each of the electrically conductive pillars. An integrated circuit incorporating a resistor construction includes, i) a layer of semiconductive material; ii) a pair of electrically conductive pillars provided within the semiconductive material layer, the pair of pillars being separated from one another and thereby having a mass of the semiconductive material extending therebetween; and iii) an electrically conductive node in electrical connection with each of the respective conductive pillars. Alternately, a resistor is provided within a semiconductive substrate using different concentration diffusion regions.

    摘要翻译： 从半导体材料形成电阻器的方法包括：a）提供衬底; b）在衬底上提供半导体材料层; c）在半导体材料层中提供一对开口; d）用导电材料堵塞所述一对开口，以在所述半导体材料内限定一对导电柱，所述一对支柱具有在其间延伸的半导体材料以提供电阻器结构; 以及e）为每个导电柱提供导电节点。 结合电阻器结构的集成电路包括：i）半导体材料层; ii）设置在半导体材料层内的一对导电柱，所述一对柱彼此分离，从而具有在其间延伸的半导体材料的质量; 以及iii）与每个相应的导电柱电连接的导电节点。 或者，使用不同的浓度扩散区域在半导体衬底内提供电阻器。

    Method of forming a resistor and integrated circuitry having a resistor construction
    7.
    发明授权
    Method of forming a resistor and integrated circuitry having a resistor construction 失效
    形成电阻器的方法和具有电阻器结构的集成电路

    公开(公告)号：US5668037A

    公开(公告)日：1997-09-16

    申请号：US679705

    申请日：1996-07-11

    申请人： Kirk Prall ,  Pierre C. Fazan ,  Aftab Ahmad ,  Howard E. Rhodes ,  Werner Juengling ,  Pai-Hung Pan ,  Tyler Lowrey

    发明人： Kirk Prall ,  Pierre C. Fazan ,  Aftab Ahmad ,  Howard E. Rhodes ,  Werner Juengling ,  Pai-Hung Pan ,  Tyler Lowrey

    IPC分类号： H01L21/02 ,  H01L27/06 ,  H01L27/08 ,  H01L21/70

    CPC分类号： H01L28/20 ,  H01L27/0629 ,  H01L27/0802 ,  Y10S148/136

    摘要： A method of forming a resistor from semiconductive material includes, a) providing a substrate; b) providing a layer of semiconductive material over the substrate; c) providing a pair of openings into the semiconductive material layer; d) plugging the pair of openings with an electrically conductive material to define a pair of electrically conductive pillars within the semiconductive material, the pair of pillars having semiconductive material extending therebetween to provide a resistor construction; and e) providing a conductive node to each of the electrically conductive pillars. An integrated circuit incorporating a resistor construction includes, i) a layer of semiconductive material; ii) a pair of electrically conductive pillars provided within the semiconductive material layer, the pair of pillars being separated from one another and thereby having a mass of the semiconductive material extending therebetween; and iii) an electrically conductive node in electrical connection with each of the respective conductive pillars. Alternately, a resistor is provided within a semiconductive substrate using different concentration diffusion regions.

    摘要翻译： 从半导体材料形成电阻器的方法包括：a）提供衬底; b）在衬底上提供半导体材料层; c）在半导体材料层中提供一对开口; d）用导电材料堵塞所述一对开口，以在所述半导体材料内限定一对导电柱，所述一对支柱具有在其间延伸的半导体材料以提供电阻器结构; 以及e）为每个导电柱提供导电节点。 结合电阻器结构的集成电路包括：i）半导体材料层; ii）设置在半导体材料层内的一对导电柱，所述一对柱彼此分离，从而具有在其间延伸的半导体材料的质量; 以及iii）与每个相应的导电柱电连接的导电节点。 或者，使用不同的浓度扩散区域在半导体衬底内提供电阻器。

    Method of forming contact plugs
    8.
    发明授权
    Method of forming contact plugs 失效
    形成接触塞的方法

    公开(公告)号：US5858865A

    公开(公告)日：1999-01-12

    申请号：US569838

    申请日：1995-12-07

    申请人： Werner Juengling ,  Kirk Prall ,  Gordon Haller ,  David Keller ,  Tyler Lowrey

    发明人： Werner Juengling ,  Kirk Prall ,  Gordon Haller ,  David Keller ,  Tyler Lowrey

    IPC分类号： H01L21/28 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L21/3205

    CPC分类号： H01L27/10888 ,  H01L21/28 ,  H01L21/768 ,  H01L21/76897 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S438/978

    摘要： Within an integrated circuit, a contact plug with a height not extending above the level of the gate/wordline nitride is nonetheless provided with a relatively large contact area or landing pad, significantly larger than the source/drain region to which the contact plug is electrically connected. Methods for producing the inventive contact plug include (1) use of a nitride facet etch, either (a) during a nitride spacer formation etch or (b) during a BPSG etch; (2) using at least one of (a) an isotropic photoresist etch or partial descum to narrow BPSG spacers above the gate/wordline nitride, and (b) a nitride step etch to etch the shoulder area of the gate/wordline nitride exposed by a BPSG etch; and (3) polishing a BPSG layer down to the top of a gate/wordline nitride before any doped polysilicon plug fill, masking for BPSG etch and performing a BPSG etch, etching the photoresist layer through a partial descum, and etching the shoulder area of the gate/wordline nitride exposed thereby.

    摘要翻译： 在集成电路中，具有不延伸在栅极/字线氮化物的高度之上的高度的接触插塞仍然设置有相对较大的接触面积或着陆焊盘，其明显大于接触插塞电接触的源极/漏极区域 连接的。 用于制造本发明接触塞的方法包括（1）在氮化物间隔物形成蚀刻期间使用氮化物刻面蚀刻（a）或（b）在BPSG蚀刻期间; （2）使用（a）各向同性光致抗蚀剂蚀刻或部分除去中的至少一种来窄化栅极/字线氮化物之上的BPSG间隔区，以及（b）氮化物步骤蚀刻以蚀刻暴露于栅极/字线氮化物的肩部区域 BPSG蚀刻; 并且（3）在任何掺杂的多晶硅插塞填充之前将BPSG层向下抛光到栅极/字线氮化物的顶部，掩蔽用于BPSG蚀刻和执行BPSG蚀刻，通过部分除去蚀刻光致抗蚀剂层，并蚀刻 栅极/字线氮化物被曝光。

    Contact plug
    9.
    发明授权
    Contact plug 有权
    接触塞

    公开(公告)号：US06469389B2

    公开(公告)日：2002-10-22

    申请号：US09567649

    申请日：2000-05-09

    申请人： Werner Juengling ,  Kirk Prall ,  Gordon Haller ,  David Keller ,  Tyler Lowrey

    发明人： Werner Juengling ,  Kirk Prall ,  Gordon Haller ,  David Keller ,  Tyler Lowrey

    IPC分类号： H01L2348

    CPC分类号： H01L27/10888 ,  H01L21/28 ,  H01L21/768 ,  H01L21/76897 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S438/978 ,  H01L2924/00

    摘要： Within an integrated circuit, a contact plug with a height not extending above the level of the gate/wordline nitride is nonetheless provided with a relatively large contact area or landing pad, significantly larger than the source/drain region to which the contact plug is electrically connected. Methods for producing the inventive contact plug include (1) use of a nitride facet etch, either (a) during a nitride spacer formation etch or (b) during a BPSG etch; (2) using at least one of (a) an isotropic photoresist etch or partial descum to narrow BPSG spacers above the gate/wordline nitride, and (b) a nitride step etch to etch the shoulder area of the gate/wordline nitride exposed by a BPSG etch; and (3) polishing a BPSG layer down to the top of a gate/wordline nitride before any doped polysilicon plug fill, masking for BPSG etch and performing a BPSG etch, etching the photoresist layer through a partial descum, and etching the shoulder area of the gate/wordline nitride exposed thereby.

    摘要翻译： 在集成电路中，具有不延伸在栅极/字线氮化物的高度之上的高度的接触插塞仍然设置有相对较大的接触面积或着陆焊盘，其明显大于接触插塞电接触的源极/漏极区域 连接的。 用于制造本发明接触塞的方法包括（1）在氮化物间隔物形成蚀刻期间使用氮化物刻面蚀刻（a）或（b）在BPSG蚀刻期间; （2）使用（a）各向同性光致抗蚀剂蚀刻或部分除去中的至少一种来窄化栅极/字线氮化物之上的BPSG间隔区，以及（b）氮化物步骤蚀刻以蚀刻暴露于栅极/字线氮化物的肩部区域 BPSG蚀刻; 并且（3）在任何掺杂的多晶硅插塞填充之前将BPSG层向下抛光到栅极/字线氮化物的顶部，掩蔽用于BPSG蚀刻和执行BPSG蚀刻，通过部分除去蚀刻光致抗蚀剂层，并蚀刻 栅极/字线氮化物被曝光。

    Self-aligned contact plugs
    10.
    发明授权
    Self-aligned contact plugs 有权
    自对准接触插头

    公开(公告)号：US6060783A

    公开(公告)日：2000-05-09

    申请号：US225593

    申请日：1999-01-06

    申请人： Werner Juengling ,  Kirk Prall ,  Gordon Haller ,  David Keller ,  Tyler Lowrey

    发明人： Werner Juengling ,  Kirk Prall ,  Gordon Haller ,  David Keller ,  Tyler Lowrey

    IPC分类号： H01L21/28 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L23/48

    CPC分类号： H01L27/10888 ,  H01L21/28 ,  H01L21/768 ,  H01L21/76897 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S438/978

    摘要： Within an integrated circuit, a contact plug with a height not extending above the level of the gate/wordline nitride is nonetheless provided with a relatively large contact area or landing pad, significantly larger than the source/drain region to which the contact plug is electrically connected. Methods for producing the inventive contact plug include (1) use of a nitride facet etch, either (a) during a nitride spacer formation etch or (b) during a BPSG etch; (2) using at least one of (a) an isotropic photoresist etch or partial descum to narrow BPSG spacers above the gate/wordline nitride, and (b) a nitride step etch to etch the shoulder area of the gate/wordline nitride exposed by a BPSG etch; and (3) polishing a BPSG layer down to the top of a gate/wordline nitride before any doped polysilicon plug fill, masking for BPSG etch and performing a BPSG etch, etching the photoresist layer through a partial descum, and etching the shoulder area of the gate/wordline nitride exposed thereby.

    摘要翻译： 在集成电路中，具有不延伸在栅极/字线氮化物的高度之上的高度的接触插塞仍然设置有相对较大的接触面积或着陆焊盘，其明显大于接触插塞电接触的源极/漏极区域 连接的。 用于制造本发明接触塞的方法包括（1）在氮化物间隔物形成蚀刻期间使用氮化物刻面蚀刻（a）或（b）在BPSG蚀刻期间; （2）使用（a）各向同性光致抗蚀剂蚀刻或部分除去中的至少一种来窄化栅极/字线氮化物之上的BPSG间隔区，以及（b）氮化物步骤蚀刻以蚀刻暴露于栅极/字线氮化物的肩部区域 BPSG蚀刻; 并且（3）在任何掺杂的多晶硅插塞填充之前将BPSG层向下抛光到栅极/字线氮化物的顶部，掩蔽用于BPSG蚀刻和执行BPSG蚀刻，通过部分除去蚀刻光致抗蚀剂层，并蚀刻 栅极/字线氮化物被曝光。