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公开(公告)号：US20070132029A1
公开(公告)日：2007-06-14
申请号：US11300710
申请日：2005-12-14
申请人： Agni Mitra , Darrell Hill , Karthik Rajagopalan , Adolfo Reyes
发明人： Agni Mitra , Darrell Hill , Karthik Rajagopalan , Adolfo Reyes
IPC分类号： H01L23/62
CPC分类号： H01L23/62 , H01L27/0248 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , Y10T29/413 , Y10T29/49204 , H01L2924/00
摘要： Methods and apparatus are provided for ESD protection of integrated passive devices (IPDs). The apparatus comprises one or more IPDs having terminals or other elements potentially exposed to ESD transients coupled by charge leakage resistances having resistance values much larger than the ordinary impedance of the IPDs at the operating frequency of interest. When the IPD is built on a semi-insulating substrate, various elements of the IPD are coupled to the substrate by spaced-apart connections so that the substrate itself provides the high value resistances coupling the elements, but this is not essential. When applied to an IPD RF coupler, the ESD tolerance increased by over 70%. The invented arrangement can also be applied to active devices and integrated circuits and to IPDs with conductive or insulating substrates.
摘要翻译： 为集成无源器件（IPD）的ESD保护提供了方法和设备。 该装置包括一个或多个IPD，其具有潜在地暴露于ESD瞬变的端子或其他元件，其通过电荷泄漏电阻耦合，其电阻值比在感兴趣的工作频率下的IPD的普通阻抗大得多。 当IPD构建在半绝缘基板上时，IPD的各种元件通过间隔开的连接件耦合到基板，使得基板本身提供耦合元件的高价值电阻，但这不是必须的。 当应用于IPD RF耦合器时，ESD耐受性提高了70％以上。 本发明的布置还可以应用于有源器件和集成电路以及具有导电或绝缘衬底的IPD。
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公开(公告)号：US20080108217A1
公开(公告)日：2008-05-08
申请号：US11972475
申请日：2008-01-10
申请人： Agni Mitra , Darrell Hill , Karthik Rajagopalan , Adolfo Reyes
发明人： Agni Mitra , Darrell Hill , Karthik Rajagopalan , Adolfo Reyes
CPC分类号： H01L23/62 , H01L27/0248 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , Y10T29/413 , Y10T29/49204 , H01L2924/00
摘要： Methods and apparatus are provided for ESD protection of integrated passive devices (IPDs). The apparatus comprises one or more IPDs having terminals or other elements potentially exposed to ESD transients coupled by charge leakage resistances having resistance values much larger than the ordinary impedance of the IPDs at the operating frequency of interest. When the IPD is built on a semi-insulating substrate, various elements of the IPD are coupled to the substrate by spaced-apart connections so that the substrate itself provides the high value resistances coupling the elements, but this is not essential. When applied to an IPD RF coupler, the ESD tolerance increased by over 70%. The invented arrangement can also be applied to active devices and integrated circuits and to IPDs with conductive or insulating substrates.
摘要翻译： 为集成无源器件（IPD）的ESD保护提供了方法和设备。 该装置包括一个或多个IPD，其具有潜在地暴露于ESD瞬变的端子或其他元件，其通过电荷泄漏电阻耦合，其电阻值比在感兴趣的工作频率下的IPD的普通阻抗大得多。 当IPD构建在半绝缘基板上时，IPD的各种元件通过间隔开的连接件耦合到基板，使得基板本身提供耦合元件的高价值电阻，但这不是必须的。 当应用于IPD RF耦合器时，ESD耐受性提高了70％以上。 本发明的布置还可以应用于有源器件和集成电路以及具有导电或绝缘衬底的IPD。
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公开(公告)号：US07642182B2
公开(公告)日：2010-01-05
申请号：US11972475
申请日：2008-01-10
IPC分类号： H01L21/44
CPC分类号： H01L23/62 , H01L27/0248 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , Y10T29/413 , Y10T29/49204 , H01L2924/00
摘要： Methods and apparatus are provided for ESD protection of integrated passive devices (IPDs). The apparatus comprises one or more IPDs having terminals or other elements potentially exposed to ESD transients coupled by charge leakage resistances having resistance values much larger than the ordinary impedance of the IPDs at the operating frequency of interest. When the IPD is built on a semi-insulating substrate, various elements of the IPD are coupled to the substrate by spaced-apart connections so that the substrate itself provides the high value resistances coupling the elements, but this is not essential. When applied to an IPD RF coupler, the ESD tolerance increased by over 70%. The invented arrangement can also be applied to active devices and integrated circuits and to IPDs with conductive or insulating substrates.
摘要翻译： 为集成无源器件（IPD）的ESD保护提供了方法和设备。 该装置包括一个或多个IPD，其具有潜在地暴露于ESD瞬变的端子或其他元件，其通过电荷泄漏电阻耦合，其电阻值比在感兴趣的工作频率下的IPD的普通阻抗大得多。 当IPD构建在半绝缘基板上时，IPD的各种元件通过间隔开的连接件耦合到基板，使得基板本身提供耦合元件的高价值电阻，但这不是必须的。 当应用于IPD RF耦合器时，ESD耐受性提高了70％以上。 本发明的布置还可以应用于有源器件和集成电路以及具有导电或绝缘衬底的IPD。
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公开(公告)号：US07335955B2
公开(公告)日：2008-02-26
申请号：US11300710
申请日：2005-12-14
IPC分类号： H01L23/62
CPC分类号： H01L23/62 , H01L27/0248 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , Y10T29/413 , Y10T29/49204 , H01L2924/00
摘要： Methods and apparatus are provided for ESD protection of integrated passive devices (IPDs). The apparatus comprises one or more IPDs having terminals or other elements potentially exposed to ESD transients coupled by charge leakage resistances having resistance values much larger than the ordinary impedance of the IPDs at the operating frequency of interest. When the IPD is built on a semi-insulating substrate, various elements of the IPD are coupled to the substrate by spaced-apart connections so that the substrate itself provides the high value resistances coupling the elements, but this is not essential. When applied to an IPD RF coupler, the ESD tolerance increased by over 70%. The invented arrangement can also be applied to active devices and integrated circuits and to IPDs with conductive or insulating substrates.
摘要翻译： 为集成无源器件（IPD）的ESD保护提供了方法和设备。 该装置包括一个或多个IPD，其具有潜在地暴露于ESD瞬变的端子或其他元件，其通过电荷泄漏电阻耦合，其电阻值比在感兴趣的工作频率下的IPD的普通阻抗大得多。 当IPD构建在半绝缘基板上时，IPD的各种元件通过间隔开的连接件耦合到基板，使得基板本身提供耦合元件的高价值电阻，但这不是必须的。 当应用于IPD RF耦合器时，ESD耐受性提高了70％以上。 本发明的布置还可以应用于有源器件和集成电路以及具有导电或绝缘衬底的IPD。
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5.发明授权III-V compound semiconductor device with a surface layer in access regions having charge of polarity opposite to channel charge and method of making the same 有权III-V族化合物半导体器件，其具有与沟道电荷极性相反的电荷的存取区域中的表面层及其制造方法公开(公告)号：US07682912B2
公开(公告)日：2010-03-23
申请号：US11554859
申请日：2006-10-31
IPC分类号： H01L21/336
CPC分类号： H01L29/66924 , H01L29/2003
摘要： A method of forming a III-V compound semiconductor structure (10) comprises providing a III-V compound semiconductor substrate including a semi-insulating substrate (12) having at least one epitaxial layer formed thereon and further having a gate insulator (14) overlying the at least one epitaxial layer. The at least one epitaxial layer formed on the semi-insulating substrate comprises an epi-structure suitable for use in the formation of a channel of a III-V compound semiconductor MOSFET device, wherein the channel (30) having a first polarity. The method further comprises forming a charge layer (22) at a surface of the gate insulator, the charge layer having a second polarity, wherein the second polarity is opposite to the first polarity.
摘要翻译： 一种形成III-V族化合物半导体结构（10）的方法包括：提供一种III-V族化合物半导体衬底，该III-V族化合物半导体衬底包括半导体衬底（12），该半绝缘衬底具有形成在其上的至少一个外延层，并且还具有覆盖 所述至少一个外延层。 形成在半绝缘衬底上的至少一个外延层包括适于用于形成III-V族化合物半导体MOSFET器件的沟道的外延结构，其中，具有第一极性的沟道（30）。 该方法还包括在栅极绝缘体的表面形成电荷层（22），电荷层具有第二极性，其中第二极性与第一极性相反。
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公开(公告)号：US20090189252A1
公开(公告)日：2009-07-30
申请号：US12022942
申请日：2008-01-30
申请人： Matthias Passlack , Jonathan K. Abrokwah , Karthik Rajagopalan , Haiping Zhou , Richard J. Hill , Xu Li , David A. Moran , Iain G. Thayne , Peter Zurcher
发明人： Matthias Passlack , Jonathan K. Abrokwah , Karthik Rajagopalan , Haiping Zhou , Richard J. Hill , Xu Li , David A. Moran , Iain G. Thayne , Peter Zurcher
IPC分类号： H01L21/334 , H01L29/20
CPC分类号： H01L29/78 , H01L29/20 , H01L29/66462 , H01L29/7785
摘要： A semiconductor fabrication process includes forming a gate dielectric layer (120) overlying a substrate (101) that includes a III-V semiconductor compound. The gate dielectric layer is patterned to produce a gate dielectric structure (121) that has a substantially vertical sidewall (127), e.g., a slope of approximately 45° to 90°. A metal contact structure (130) is formed overlying the wafer substrate. The contact structure is laterally displaced from the gate dielectric structure sufficiently to define a gap (133) between the two. The wafer (100) is heat treated, which causes migration of at least one of the metal elements to form an alloy region (137) in the underlying wafer substrate. The alloy region underlies the contact structure and extends across all or a portion of the wafer substrate underlying the gap. An insulative or dielectric capping layer (140,150) is then formed overlying the wafer and covering the portion of the substrate exposed by the gap.
摘要翻译： 半导体制造工艺包括形成覆盖在包括III-V半导体化合物的衬底（101）上的栅极电介质层（120）。 栅极介电层被图案化以产生具有基本上垂直的侧壁（127）的栅极电介质结构（121），例如大约45°至90°的斜率。 金属接触结构（130）形成在晶片衬底上。 接触结构被充分地从栅极电介质结构侧向移位以限定两者之间的间隙（133）。 对晶片（100）进行热处理，这导致至少一种金属元素迁移，从而在下面的晶片衬底中形成合金区域（137）。 合金区域位于接触结构的下面，并且延伸穿过位于间隙下方的晶片衬底的全部或一部分。 然后形成绝缘或介电覆盖层（140,150），覆盖晶片并覆盖由间隙暴露的衬底的部分。
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公开(公告)号：US08503588B2
公开(公告)日：2013-08-06
申请号：US12611810
申请日：2009-11-03
申请人： Wei Luo , Karthik Rajagopalan , Andrew du Preez , Bin Liu , Shuangquan Wang
发明人： Wei Luo , Karthik Rajagopalan , Andrew du Preez , Bin Liu , Shuangquan Wang
CPC分类号： H04B1/7107
摘要： Aspects of a method and system for compensation of interference cancellation delay are provided. In this regard, a wireless communication device may receive one or more signals and may be operable to select, whether dynamically or statically, a processing path for processing the one or more received signals. The selected processing path may comprise one of an interference cancellation processing path and a pass-through processing path. A delay introduced by the pass-through processing path may be approximately equal to a processing delay introduced by the interference cancellation processing path. The one or more received signals may comprise HSDPA signals. The selection of processing path may be based on a measure of interference present in the one or more received signals.
摘要翻译： 提供了一种用于补偿干扰消除延迟的方法和系统。 在这方面，无线通信设备可以接收一个或多个信号，并且可以可操作地动态地或静态地选择用于处理一个或多个接收信号的处理路径。 所选择的处理路径可以包括干扰消除处理路径和直通处理路径之一。 由直通处理路径引入的延迟可以近似等于由干扰消除处理路径引入的处理延迟。 一个或多个接收信号可以包括HSDPA信号。 处理路径的选择可以基于存在于一个或多个接收信号中的干扰的度量。
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公开(公告)号：US07799647B2
公开(公告)日：2010-09-21
申请号：US11831394
申请日：2007-07-31
IPC分类号： H01L21/336 , H01L31/00
CPC分类号： H01L29/155 , H01L29/66462
摘要： A method of forming a semiconductor structure includes forming a channel layer; forming a superlattice barrier layer overlying the channel layer, and forming a gate dielectric overlying the superlattice barrier layer. The superlattice barrier layer includes alternating first and second layers of barrier material. In addition, the superlattice barrier layer is configured for increasing a transconductance of the semiconductor device by at least a factor of three over a semiconductor device absent such superlattice barrier layer.
摘要翻译： 形成半导体结构的方法包括形成沟道层; 形成覆盖所述沟道层的超晶格势垒层，以及形成覆盖所述超晶格势垒层的栅极电介质。 超晶格势垒层包括交替的第一和第二层屏障材料。 此外，超晶格势垒层被配置为在没有这种超晶格势垒层的半导体器件上将半导体器件的跨导增加至少三分之一。
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公开(公告)号：US20090032802A1
公开(公告)日：2009-02-05
申请号：US11831394
申请日：2007-07-31
IPC分类号： H01L29/15 , H01L21/336
CPC分类号： H01L29/155 , H01L29/66462
摘要： A method of forming a semiconductor structure comprises forming a channel layer; forming a superlattice barrier layer overlying the channel layer, and forming a gate dielectric overlying the superlattice barrier layer. The superlattice barrier layer includes a plurality of alternating first and second layers of barrier material. In addition, the superlattice barrier layer is configured for increasing a transconductance of the semiconductor device by at least a factor of three over a semiconductor device absent such superlattice barrier layer.
摘要翻译： 形成半导体结构的方法包括形成沟道层; 形成覆盖所述沟道层的超晶格势垒层，以及形成覆盖所述超晶格势垒层的栅极电介质。 超晶格阻挡层包括多个交替的第一和第二层屏障材料。 此外，超晶格势垒层被配置为在没有这种超晶格势垒层的半导体器件上将半导体器件的跨导增加至少三分之一。
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10.发明申请公开(公告)号：US20070090405A1
公开(公告)日：2007-04-26
申请号：US11236187
申请日：2005-09-27
IPC分类号： H01L23/58
CPC分类号： H01L29/66462 , H01L21/02178 , H01L21/02222 , H01L21/02362 , H01L21/28264 , H01L21/318 , H01L29/517 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a semiconductor structure comprises providing an insulator layer overlying a III-V compound substrate, the insulator layer having a surface charge layer, the surface charge layer having a deleterious performance effect on the underlying layer or layers of the III-V compound substrate. The method further comprises transforming the surface charge layer into a passivated surface layer, wherein the passivated surface layer reduces the deleterious performance effect on the underlying layer or layers.
摘要翻译： 形成半导体结构的方法包括提供覆盖III-V复合衬底的绝缘体层，所述绝缘体层具有表面电荷层，所述表面电荷层对III-V族化合物的下层或多层具有有害的性能作用 基质。 该方法还包括将表面电荷层转化为钝化表面层，其中钝化表面层减少对下层或下层的有害性能影响。
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