公开(公告)号：US06812751B2

公开(公告)日：2004-11-02

申请号：US10271952

申请日：2002-10-15

申请人： Agustinus Sutandi ,  Daran DeShazo ,  Jason Stevens ,  Craig Waller

发明人： Agustinus Sutandi ,  Daran DeShazo ,  Jason Stevens ,  Craig Waller

IPC分类号： H03K1722

CPC分类号： H03K17/223 ,  H03K2217/0036

摘要： A low standby current power-on reset circuit is described. A first NMOS transistor's drain is coupled to a first PMOS transistor's drain; source coupled to ground line; and gate coupled to a first capacitor coupled to ground line. The first PMOS transistor's source is coupled to power line; gate coupled to second capacitor coupled to ground line; and drain provides a power-on reset indication. A second PMOS transistor's source is coupled to power line; drain is coupled to drain of second NMOS transistor, gates of first PMOS, second PMOS, and second NMOS transistors, and second capacitor. The second NMOS transistor's source is coupled to gate of first NMOS transistor and first capacitor. A discharge circuit is coupled to power line, ground line, and first and second capacitors for discharging the capacitors when a voltage on power line drops below a level determined by the second PMOS transistor's threshold voltage.

公开(公告)号：US06741500B2

公开(公告)日：2004-05-25

申请号：US10264756

申请日：2002-10-04

申请人： Daran DeShazo ,  Agustinus Sutandi ,  Jason Stevens

发明人： Daran DeShazo ,  Agustinus Sutandi ,  Jason Stevens

IPC分类号： G11C1600

CPC分类号： G11C16/0441 ,  G11C17/14

摘要： An OTP bit cell includes a latch circuit of cross-coupled inverters. A floating gate PMOS transistor is inserted in each of the inverters. One or the other of the floating gate PMOS transistors is programmed through an included programming circuit so that a differential output of the latch circuit provides a corresponding logic state that is the same each time when read. To program a selected floating gate PMOS transistor, appropriate write inputs are applied to the programming circuit while a high reference voltage to the OTP bit cell is raised to a level such that the selected floating gate PMOS transistor is programmed.

摘要翻译： OTP位单元包括交叉耦合的反相器的锁存电路。 在每个逆变器中插入浮置栅极PMOS晶体管。 一个或另一个浮置栅极PMOS晶体管通过包含的编程电路进行编程，使得锁存电路的差分输出提供相应的每次读取时相同的逻辑状态。 为了对所选择的浮置栅极PMOS晶体管进行编程，适当的写入输入被施加到编程电路，同时向OTP位单元的高参考电压升高到使所选择的浮置栅极PMOS晶体管被编程的电平。

公开(公告)号：US08400208B2

公开(公告)日：2013-03-19

申请号：US13326162

申请日：2011-12-14

申请人： Agustinus Sutandi ,  Yanyi L. Wong

发明人： Agustinus Sutandi ,  Yanyi L. Wong

IPC分类号： H03K17/687

CPC分类号： H03K17/102 ,  H03K3/356121

摘要： Switch circuits are disclosed, for providing a single-ended and a differentially switched high-voltage output signals by switching a high supply voltage in response to at least one logic-level control signal. The switch that provides the single-ended switched high-voltage output signal includes a chain of at least three serially coupled field effect transistors (FETs). The chain receives the high supply voltage and switches it to output the high-voltage output signal. The switch that provides the differentially switched high-voltage output signal includes two differentially coupled chains, each having at least three serially coupled FETs. The chains receive the high supply voltage and switch it to output the differential high-voltage output signal. A control/bias circuit provides a control voltage to at least one of the FETs in the chains, responsive to the control signal.

摘要翻译： 公开了开关电路，用于通过响应于至少一个逻辑电平控制信号切换高电源电压来提供单端和差分开关的高电压输出信号。 提供单端开关高压输出信号的开关包括至少三个串联耦合场效应晶体管（FET）的链。 链条接收高电源电压并切换以输出高电压输出信号。 提供差分开关高压输出信号的开关包括两个差分耦合的链，每个链具有至少三个串联耦合的FET。 链条接收高电源电压并将其切换以输出差分高压输出信号。 响应于控制信号，控制/偏置电路向链中的至少一个FET提供控制电压。

公开(公告)号：US20130015831A1

公开(公告)日：2013-01-17

申请号：US13183473

申请日：2011-07-15

申请人： Yanyi L. WONG ,  Agustinus Sutandi

发明人： Yanyi L. WONG ,  Agustinus Sutandi

IPC分类号： G05F1/10

CPC分类号： H02M3/07 ,  H01G5/40 ,  H02M2001/0022

摘要： Voltage regulation in charge pumps. A high voltage generation system includes a charge pump having an output voltage node and a regulated input voltage node. The high voltage generation system also includes a voltage regulator. The voltage regulator includes a capacitive attenuator in electrical communication with the output voltage node. The voltage regulator also includes a comparator in electrical communication with the capacitive attenuator and with a reference voltage source. The voltage regulator further includes a buffer in electrical communication between the comparator and the regulated input voltage node.

摘要翻译： 电荷泵电压调节。 高压发电系统包括具有输出电压节点和调节输入电压节点的电荷泵。 高电压发生系统还包括电压调节器。 电压调节器包括与输出电压节点电连通的电容衰减器。 电压调节器还包括与电容衰减器和参考电压源电连通的比较器。 电压调节器还包括在比较器和调节输入电压节点之间电连通的缓冲器。

公开(公告)号：US07724571B1

公开(公告)日：2010-05-25

申请号：US11982278

申请日：2007-10-31

申请人： Chad A. Lindhorst ,  Todd E. Humes ,  Alex May ,  Agustinus Sutandi

发明人： Chad A. Lindhorst ,  Todd E. Humes ,  Alex May ,  Agustinus Sutandi

IPC分类号： G11C14/00

CPC分类号： G11C5/145 ,  G11C7/1006 ,  G11C16/10 ,  G11C16/30

摘要： Adaptive programming methods and supportive device architecture for memory devices are provided. Methods include partitioning words into variable length segments. More particularly, methods include receiving a word of data, parsing the word into a plurality of write-subsets, where the size of the write-subsets depends on values of the data and constraints that are specific to the memory circuit, and writing the data in cells of the memory circuit, one write-subset at a time. A memory device includes a digital controller capable of parsing words into a plurality of write-subsets, where the length of write-subsets are depending on values of the data and constraints that are specific to the memory device.

摘要翻译： 提供了自适应编程方法和用于存储器件的支持器件架构。 方法包括将字划分成可变长度段。 更具体地，方法包括接收数据字，将字解析成多个写子集，其中写子集的大小取决于数据的值和存储电路特有的约束，以及写数据 在存储器电路的单元中，一次写入子集。 存储器装置包括能够将字解析为多个写子集的数字控制器，其中写子集的长度取决于数据的值和对存储器件特有的约束。

公开(公告)号：US08937464B2

公开(公告)日：2015-01-20

申请号：US13183473

申请日：2011-07-15

申请人： Yanyi L. Wong ,  Agustinus Sutandi

发明人： Yanyi L. Wong ,  Agustinus Sutandi

IPC分类号： G05F1/00 ,  H02M3/18 ,  H02M3/07 ,  H01G5/40 ,  H02M1/00

CPC分类号： H02M3/07 ,  H01G5/40 ,  H02M2001/0022

摘要： Voltage regulation in charge pumps. A high voltage generation system includes a charge pump having an output voltage node and a regulated input voltage node. The high voltage generation system also includes a voltage regulator. The voltage regulator includes a capacitive attenuator in electrical communication with the output voltage node. The voltage regulator also includes a comparator in electrical communication with the capacitive attenuator and with a reference voltage source. The voltage regulator further includes a buffer in electrical communication between the comparator and the regulated input voltage node.

摘要翻译： 电荷泵电压调节。 高压发电系统包括具有输出电压节点和调节输入电压节点的电荷泵。 高电压发生系统还包括电压调节器。 电压调节器包括与输出电压节点电连通的电容衰减器。 电压调节器还包括与电容衰减器和参考电压源电连通的比较器。 电压调节器还包括在比较器和调节输入电压节点之间电连通的缓冲器。

公开(公告)号：US07724570B1

公开(公告)日：2010-05-25

申请号：US11982277

申请日：2007-10-31

申请人： Chad A. Lindhorst ,  Todd E. Humes ,  Alex May ,  Agustinus Sutandi

发明人： Chad A. Lindhorst ,  Todd E. Humes ,  Alex May ,  Agustinus Sutandi

IPC分类号： G11C14/00

CPC分类号： G11C5/145 ,  G11C7/1006 ,  G11C16/10 ,  G11C16/30

摘要： Adaptive programming methods and supportive device architecture for memory devices are provided. Methods include partitioning words into variable length segments. More particularly, methods include receiving a word of data, parsing the word into a plurality of write-subsets, where the size of the write-subsets depends on values of the data and constraints that are specific to the memory circuit, and writing the data in cells of the memory circuit, one write-subset at a time. A memory device includes a digital controller capable of parsing words into a plurality of write-subsets, where the length of write-subsets are depending on values of the data and constraints that are specific to the memory device.

摘要翻译： 提供了自适应编程方法和用于存储器件的支持器件架构。 方法包括将字划分成可变长度段。 更具体地，方法包括接收数据字，将字解析成多个写子集，其中写子集的大小取决于数据的值和存储电路特有的约束，以及写数据 在存储器电路的单元中，一次写入子集。 存储器装置包括能够将字解析为多个写子集的数字控制器，其中写子集的长度取决于数据的值和对存储器件特有的约束。

公开(公告)号：US08729883B2

公开(公告)日：2014-05-20

申请号：US13171491

申请日：2011-06-29

申请人： Yanyi L. Wong ,  Agustinus Sutandi

发明人： Yanyi L. Wong ,  Agustinus Sutandi

IPC分类号： G05F3/04

CPC分类号： G05F3/262 ,  G05F3/265

摘要： A current source with low power consumption and reduced on-chip area occupancy. The current source for providing a constant current to a load includes a first circuit that generates a reference current. The first circuit includes a first plurality of interconnected transistors. The current source also includes a characteristic resistor, coupled to the first circuit, that determines value of the reference current. The current source further includes a second circuit and a third circuit. The second circuit, coupled to the first circuit and to the load, generates an output current that is identical to the reference current. The second circuit includes a second plurality of interconnected transistors. The third circuit, coupled to the first circuit, drives a multiple of the reference current into the characteristic resistor. The third circuit includes a third plurality of interconnected transistors.

摘要翻译： 电流源，功耗低，片上占用空间小。 用于向负载提供恒定电流的电流源包括产生参考电流的第一电路。 第一电路包括第一多个互连晶体管。 电流源还包括耦合到第一电路的特性电阻器，其确定参考电流的值。 电流源还包括第二电路和第三电路。 耦合到第一电路和负载的第二电路产生与参考电流相同的输出电流。 第二电路包括第二多个互连的晶体管。 耦合到第一电路的第三电路将参考电流的倍数驱动到特征电阻器中。 第三电路包括第三多个互连晶体管。

公开(公告)号：US20130002228A1

公开(公告)日：2013-01-03

申请号：US13171491

申请日：2011-06-29

申请人： Yanyi L. WONG ,  Agustinus Sutandi

发明人： Yanyi L. WONG ,  Agustinus Sutandi

IPC分类号： G05F3/16

CPC分类号： G05F3/262 ,  G05F3/265

摘要： A current source with low power consumption and reduced on-chip area occupancy. The current source for providing a constant current to a load includes a first circuit that generates a reference current. The first circuit includes a first plurality of interconnected transistors. The current source also includes a characteristic resistor, coupled to the first circuit, that determines value of the reference current. The current source further includes a second circuit and a third circuit. The second circuit, coupled to the first circuit and to the load, generates an output current that is identical to the reference current. The second circuit includes a second plurality of interconnected transistors. The third circuit, coupled to the first circuit, drives a multiple of the reference current into the characteristic resistor. The third circuit includes a third plurality of interconnected transistors.

摘要翻译： 电流源，功耗低，片上占用空间小。 用于向负载提供恒定电流的电流源包括产生参考电流的第一电路。 第一电路包括第一多个互连晶体管。 电流源还包括耦合到第一电路的特性电阻器，其确定参考电流的值。 电流源还包括第二电路和第三电路。 耦合到第一电路和负载的第二电路产生与参考电流相同的输出电流。 第二电路包括第二多个互连的晶体管。 耦合到第一电路的第三电路将参考电流的倍数驱动到特征电阻器中。 第三电路包括第三多个互连晶体管。

公开(公告)号：US20120086498A1

公开(公告)日：2012-04-12

申请号：US13326162

申请日：2011-12-14

申请人： Agustinus Sutandi ,  Yanyi L. Wong

发明人： Agustinus Sutandi ,  Yanyi L. Wong

IPC分类号： H03K17/687

CPC分类号： H03K17/102 ,  H03K3/356121

摘要： Switch circuits are disclosed, for providing a single-ended and a differentially switched high-voltage output signals by switching a high supply voltage in response to at least one logic-level control signal. The switch that provides the single-ended switched high-voltage output signal includes a chain of at least three serially coupled field effect transistors (FETs). The chain receives the high supply voltage and switches it to output the high-voltage output signal. The switch that provides the differentially switched high-voltage output signal includes two differentially coupled chains, each having at least three serially coupled FETs. The chains receive the high supply voltage and switch it to output the differential high-voltage output signal. A control/bias circuit provides a control voltage to at least one of the FETs in the chains, responsive to the control signal.

摘要翻译： 公开了开关电路，用于通过响应于至少一个逻辑电平控制信号切换高电源电压来提供单端和差分开关的高电压输出信号。 提供单端开关高压输出信号的开关包括至少三个串联耦合场效应晶体管（FET）的链。 链条接收高电源电压并切换以输出高电压输出信号。 提供差分开关高压输出信号的开关包括两个差分耦合的链，每个链具有至少三个串联耦合的FET。 链条接收高电源电压并将其切换以输出差分高压输出信号。 响应于控制信号，控制/偏置电路向链中的至少一个FET提供控制电压。