公开(公告)号：US5276635A

公开(公告)日：1994-01-04

申请号：US69646

申请日：1993-06-01

申请人： Ajay Naini ,  William C. Anderson

发明人： Ajay Naini ,  William C. Anderson

IPC分类号： G06F7/50 ,  G06F7/508

CPC分类号： G06F7/508

摘要： A carry look-ahead (CLA) adder accommodates a late carry-in from a low-order external 32-bit adder to enable a 96-bit addition to be performed in the same time in which the CLA adder (60) performs a 64-bit addition. Within each adder slice, intermediate group propagate and group generate terms are generated for each bit location in the adder (60), while the adder simultaneously generates an n-bit group propagate and group generate term. The intermediate group propagate and group generate terms are combined with carry-in terms to generate, in parallel, local carry-out terms within each adder slice. The local carry-out terms and intermediate group propagate and group generate terms are used to form a carry chain path which allows the adder to delay the carry-in of an external carry term.

摘要翻译： 进位预读（CLA）加法器适用于从低位外部32位加法器的延迟进位，以使得能够在CLA加法器（60）执行64位的同一时间执行96位加法运算 - 除此之外。 在每个加法器切片内，对加法器（60）中的每个比特位置生成中间组传播和组生成项，而加法器同时生成n位组传播和组生成项。 中间组传播和组生成项与进位项组合，以在每个加法器切片内并行生成局部进位项。 本地进位项和中间组传播和组生成术语用于形成进位链路径，允许加法器延迟外部进位项的进位。

公开(公告)号：US5265043A

公开(公告)日：1993-11-23

申请号：US9435

申请日：1993-01-27

申请人： Ajay Naini ,  William C. Anderson ,  Lisa J. Craft

发明人： Ajay Naini ,  William C. Anderson ,  Lisa J. Craft

IPC分类号： G06F7/52 ,  G06F7/533

CPC分类号： G06F7/5318 ,  G06F7/5338

摘要： A Wallace tree multiplier array (40) performs multiply operations using operands received via a data path (42) having a predetermined height. Rows of carry save adders (CSAs 15'-19") add sets of partial products to generate sets of intermediate summands, which are recursively added to generate a set of final summands. A first group of CSAs form a column which is placed along an axis parallel to the data path (42), and are used to compute a more significant number of bits of each of the summands. The column height of the first group of CSAs is equal to and aligned with the height of the data path (42). A second group of CSAs are placed along an axis perpendicular to the column formed by the first group of CSAs, thereby minimizing the dimension of the multiplier along the data path. The second group of CSAs compute a less significant number of bits of the summands.

摘要翻译： 华莱士树乘法器阵列（40）使用经由具有预定高度的数据路径（42）接收的操作数来执行乘法运算。 进位保存加法器（CSA 15'-19“）的行添加一组部分乘积以生成中间求和集，其被递归地添加以生成一组最终的求和。 第一组CSA形成沿着与数据路径（42）平行的轴放置的列，并且用于计算每个总和的更多有效位数。 第一组CSA的列高度等于并与数据路径（42）的高度对齐。 第二组CSA沿着垂直于由第一组CSA组形成的列的轴放置，从而使沿着数据路径的乘法器的尺寸最小化。 第二组CSA计算总和的比特数较少。

公开(公告)号：US5220525A

公开(公告)日：1993-06-15

申请号：US787477

申请日：1991-11-04

申请人： William C. Anderson ,  Ajay Naini

发明人： William C. Anderson ,  Ajay Naini

IPC分类号： G06F7/52

CPC分类号： G06F7/5338

摘要： A recorded iterative multiplier (20) performs an unsigned multiplication operation quickly and with a minimal amount of added circuitry. Multiplier (20) includes a Modified Booth recoder (34) and a plurality of multiplexors (24, 26, 28, 30, and 32) to provide a plurality of partial products. An additional partial product typically generated during a first iteration of the multiplication operation is provided to a multiplexor (44) and a remaining portion of partial products are provided to a summation tree (40) having a symmetrical circuit layout. [Multiplexor (44) stores the additional partial product until summation tree (40) has processed the remaining partial products to provide a first sum.] When summation tree (40) has processed the remaining partial products to provide a first sum, multiplexor (44) provides the additional partial product to a carry save adder (42). The first sum is added to the additional partial product in [a carry-save] adder (42) to provide a first portion of a product. During a second iteration of the multiplication operation, an additional partial product is not generated, and summation tree (40) provides the second portion of the multiplication product. The first and second portions are then summed in carry-save adder (42) to provide the multiplication product.

摘要翻译： 记录的迭代乘法器（20）快速执行无符号乘法运算，并以最小量的附加电路执行。 乘法器（20）包括修改的展位重新编码器（34）和多个多路复用器（24,26,28,30和32），以提供多个部分乘积。 通常在乘法运算的第一迭代期间产生的附加部分乘积被提供给多路复用器（44），并且部分乘积的剩余部分被提供给具有对称电路布局的求和树（40）。 多路复用器（44）存储额外的部分乘积，直到求和树（40）已经处理剩余的部分乘积以提供第一和。]当求和树（40）已经处理剩余的部分乘积以提供第一和时，多路复用器 ）向进位保存加法器（42）提供额外的部分乘积。 将第一和加到[进位保存]加法器（42）中的附加部分乘积以提供乘积的第一部分。 在乘法运算的第二次迭代期间，不产生附加的部分乘积，并且求和树（40）提供乘积的第二部分。 然后，第一和第二部分在进位保存加法器（42）中相加以提供乘积。

公开(公告)号：US08533530B2

公开(公告)日：2013-09-10

申请号：US11560332

申请日：2006-11-15

申请人： Lucian Codrescu ,  William C. Anderson ,  Suresh Venkumahanti ,  Louis Achille Giannini ,  Manojkumar Pyla ,  Xufeng Chen

发明人： Lucian Codrescu ,  William C. Anderson ,  Suresh Venkumahanti ,  Louis Achille Giannini ,  Manojkumar Pyla ,  Xufeng Chen

IPC分类号： G06F11/00

CPC分类号： G06F11/3656

摘要： Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Trusted and untrusted debugging operational control occurs in operating a core processor associated with the digital signal processor. A debugging process within a debugging mechanism associates with the core processor. The core processor process determines the origin of debugging control as trusted debugging control or untrusted debugging control. In the event of trusted debugging control, the core processor process provides to the trusted debugging control a first set of features and privileges. Alternatively, in the event that debugging control is untrusted debugging control, the core processor process provides the untrusted debugging control a second restricted set of features and privileges, all for maintaining security and proper operation of the core processor process.

摘要翻译： 用于设计和使用数字信号处理器的技术，包括（但不限于）用于处理通信（例如，CDMA）系统中的传输。 在操作与数字信号处理器相关联的核心处理器时，发生信任和不信任的调试操作控制。 调试机制中的调试过程与核心处理器相关联。 核心处理器过程将调试控制的起源确定为可信的调试控制或不可信的调试控制。 在受信任的调试控制的情况下，核心处理器进程向受信任的调试控制提供了第一组功能和特权。 或者，如果调试控制是不可信任的调试控制，则核心处理器进程将不可信任的调试控制提供第二个受限制的特征和特权集，以保持核心处理器进程的安全性和正常运行。

公开(公告)号：US20120297256A1

公开(公告)日：2012-11-22

申请号：US13112132

申请日：2011-05-20

申请人： Erich James Plondke ,  Lucian Codrescu ,  William C. Anderson

发明人： Erich James Plondke ,  Lucian Codrescu ,  William C. Anderson

IPC分类号： G06F12/00 ,  G06F11/16 ,  G06F12/08

CPC分类号： G06F12/0893 ,  G06F11/1064 ,  G06F12/0646 ,  Y02D10/13

摘要： Systems and method for configuring a page-based memory device without pre-existing dedicated metadata. The method includes reading metadata from a metadata portion of a page of the memory device, and determining a characteristic of the page based on the metadata. The memory device may be configured as a cache. The metadata may include address tags, such that determining the characteristic may include determining if desired information is present in the page, and reading the desired information if it is determined to be present in the page. The metadata may also include error-correcting code (ECC), such that determining the characteristic may include detecting errors present in data stored in the page. The metadata may further include directory information, memory coherency information, or dirty/valid/lock information.

摘要翻译： 用于配置基于页面的存储设备而不具有预先存在的专用元数据的系统和方法。 该方法包括从存储设备的页面的元数据部分读取元数据，以及基于元数据确定页面的特性。 存储器件可以被配置为高速缓存。 元数据可以包括地址标签，使得确定特征可以包括确定页面中是否存在所需信息，并且如果确定存在于页面中则读取所需信息。 元数据还可以包括纠错码（ECC），使得确定特性可以包括检测存在于页面中的数据中存在的错误。 元数据还可以包括目录信息，存储器一致性信息或脏/有效/锁定信息。

公开(公告)号：US07814487B2

公开(公告)日：2010-10-12

申请号：US11115917

申请日：2005-04-26

申请人： Lucian Codrescu ,  Erich Plondke ,  Muhammad Ahmed ,  William C. Anderson

发明人： Lucian Codrescu ,  Erich Plondke ,  Muhammad Ahmed ,  William C. Anderson

IPC分类号： G06F9/46 ,  G06F11/00 ,  G06F15/00

CPC分类号： G06F9/3851 ,  G06F9/3853

摘要： A multithreaded processor device is disclosed and includes a first program thread and second program thread. The second program thread is execution linked to the first program thread in a lock step manner. As such, when the first program thread experiences a stall event, the second program thread is instructed to perform a no operation instruction in order to keep the second program thread execution linked to the first program thread. Also, the second program thread performs a no operation instruction during each clock cycle that the first program thread is stalled due to the stall event. When the first program thread performs a first successful operation after the stall event, the second program thread restarts normal execution.

摘要翻译： 公开了一种多线程处理器设备，并且包括第一程序线程和第二程序线程。 第二个程序线程以锁定步骤的方式执行链接到第一个程序线程。 这样，当第一程序线程经历停顿事件时，指示第二程序线程执行无操作指令，以便使第二程序线程执行与第一程序线程相关联。 此外，第二程序线程在每个时钟周期期间执行无操作指令，由于失速事件使第一程序线程停滞。 当第一程序线程在停止事件之后执行第一次成功操作时，第二程序线程重新启动正常执行。

公开(公告)号：US07526633B2

公开(公告)日：2009-04-28

申请号：US11088607

申请日：2005-03-23

申请人： Lucian Codrescu ,  Erich Plondke ,  Muhammad Ahmed ,  William C. Anderson

发明人： Lucian Codrescu ,  Erich Plondke ,  Muhammad Ahmed ,  William C. Anderson

IPC分类号： G06F9/30 ,  G06F15/00

CPC分类号： G06F9/30149 ,  G06F9/3853

摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system. The method and system encode and process instructions of mixed lengths (e.g., 16 bits and 32 bits) and instruction packets including instructions of mixed lengths. This includes encoding a plurality of instructions of a first length and a plurality of instructions of a second length. The method and system encode a header having at least one instruction length bit. The instruction bit distinguishes between instructions of the first length and instructions of the second length for an associated DSP to process in a mixed stream. The method and system distinguish between the instructions of the first length and the instructions of the second length according to the contents of the instruction length bits. The header further includes bits for distinguishing between instructions of varying lengths in an instruction packet.

摘要翻译： 用于在通信（例如，CDMA）系统中处理传输的技术。 该方法和系统编码和处理混合长度（例如，16位和32位）的指令以及包括混合长度指令的指令包。 这包括编码第一长度的多个指令和第二长度的多个指令。 该方法和系统对具有至少一个指令长度位的报头进行编码。 指令位区分第一长度的指令和第二长度的指令，以使相关的DSP在混合流中进行处理。 方法和系统根据指令长度位的内容区分第一长度的指令和第二长度的指令。 标题还包括用于区分指令包中不同长度的指令的位。

公开(公告)号：US07383420B2

公开(公告)日：2008-06-03

申请号：US11089619

申请日：2005-03-24

申请人： Erich Plondke ,  Lucian Codrescu ,  Muhammad Ahmed ,  William C. Anderson

发明人： Erich Plondke ,  Lucian Codrescu ,  Muhammad Ahmed ,  William C. Anderson

IPC分类号： G06F9/26 ,  G06F9/34

CPC分类号： G06F9/35 ,  G06F9/3851 ,  G06F9/3853

摘要： A processor is operable to carry out a method that comprises accessing a first register based on a program instruction and obtaining a first register-out value, accessing a second register based on the first register-out value and obtaining a second register-out value, and storing the second register-out value into a third register based on the program instruction. The processor is further operable to carry out a method that comprises accessing a first register based on a program instruction and obtaining a first register-out value, accessing a second register based on the program instruction and obtaining a second register-out value, and storing the first register-out value into a third register based on the second register-out value.

摘要翻译： 处理器可操作以执行一种方法，该方法包括基于程序指令访问第一寄存器并获得第一寄存器值，基于第一寄存器输出值访问第二寄存器并获得第二寄存器值， 以及基于所述程序指令将所述第二寄存器值存储到第三寄存器中。 处理器还可操作以执行一种方法，该方法包括基于程序指令访问第一寄存器并获得第一寄存器值，基于所述程序指令访问第二寄存器并获得第二寄存器值，以及存储 基于第二寄存器值将第一寄存器值输入到第三寄存器中。

公开(公告)号：US20080114972A1

公开(公告)日：2008-05-15

申请号：US11560344

申请日：2006-11-15

申请人： Lucian Codrescu ,  William C. Anderson ,  Suresh Venkumahanti ,  Louis Achille Giannini ,  Manojkumar Pyla ,  Xufeng Chen

发明人： Lucian Codrescu ,  William C. Anderson ,  Suresh Venkumahanti ,  Louis Achille Giannini ,  Manojkumar Pyla ,  Xufeng Chen

IPC分类号： G06F15/163

CPC分类号： G06F11/362 ,  G06F11/3656

摘要： Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Stuffing instructions in a processing pipeline of a multi-threaded digital signal processor provides for operating a core processor process and a debugging process within a debugging mechanism. Writing a stuff instruction into a debugging process registry and a stuff command in a debugging process command register provides for identifying a predetermined thread of the multi-threaded digital signal processor in which to execute the stuff instruction. The instruction stuffing process issues a debugging process control resume command during a predetermined stage of executing on the predetermined thread and directs the core processor to perform the stuff instruction during the debugging process. The core processor may then execute the stuffed instruction in association with the core processor process and the debugging process.

摘要翻译： 用于设计和使用数字信号处理器的技术，包括（但不限于）用于处理通信（例如，CDMA）系统中的传输。 在多线程数字信号处理器的处理流水线中的填充指令提供了在调试机制内操作核心处理器进程和调试过程。 将填充指令写入调试进程注册表，并且调试进程命令寄存器中的填充命令用于标识执行填充指令的多线程数字信号处理器的预定线程。 指令填充处理在预定线程的预定执行阶段发出调试过程控制恢复命令，并指示核心处理器在调试过程中执行填充指令。 核心处理器然后可以与核心处理器进程和调试过程相关联地执行填充指令。

公开(公告)号：US5619711A

公开(公告)日：1997-04-08

申请号：US267740

申请日：1994-06-29

申请人： William C. Anderson

发明人： William C. Anderson

IPC分类号： G06F7/57 ,  G06F9/30 ,  G06F15/00

CPC分类号： G06F7/483 ,  G06F9/30025 ,  G06F2207/382

摘要： A data processing system 10 comprises an arbitrary precision number C++ class program code 18, which incorporates arbitrary precision arithmetic. The arbitrary precision number program code 18 resides in a client program 14 and never lose bits of precision by maintaining an internal data structure 16, which holds the data, and by manipulating that data by operators and methods which the program code 18 defines. The program code 18, which is embedded in a client program 14, comprises a method that uses "lazy" storage allocation for transparent data management for the arbitrary precision number in the internal data array 22, a "lazy" arithmetic evaluation for avoiding more costly arithmetic operations, a width method for an optimized significant bit calculation, and a method for efficient determining the number of trailing zeros method for more efficient IEEE floating point math emulation operations.

摘要翻译： 数据处理系统10包括任意精度数C ++类程序代码18，其包含任意精度算术。 任意精度数程序代码18驻留在客户端程序14中，并且通过维护保存数据的内部数据结构16以及通过程序代码18定义的操作符和方法操纵数据，而不会丢失精度位。 嵌入在客户机程序14中的程序代码18包括使用“惰性”存储分配用于内部数据阵列22中的任意精度数字的透明数据管理的方法，用于避免更昂贵的“懒惰”算术评估 算术运算，用于优化的有效位计算的宽度方法，以及用于有效确定用于更有效的IEEE浮点数学仿真操作的尾随零方法的数量的方法。