公开(公告)号：US08552506B2

公开(公告)日：2013-10-08

申请号：US13492515

申请日：2012-06-08

申请人： Akihiro Usujima ,  Shigeo Satoh

发明人： Akihiro Usujima ,  Shigeo Satoh

IPC分类号： H01L27/092

CPC分类号： H01L21/823892 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823807 ,  H01L21/823878

摘要： A method of manufacturing a semiconductor device includes forming a first and a second isolation insulating film to define a first, a second, a third and a fourth region, forming a first insulating film, implanting a first impurity of a first conductivity type through the first insulating film into the first, the second and the fourth region at a first depth, forming a second insulating film thinner than the first insulating film, implanting a second impurity of a second conductivity type through the second insulating film into the third region at a second depth in the semiconductor substrate, implanting a third impurity of the second conductivity type into the third region at a third depth shallower than the second depth, forming a first transistor of the first conductivity type in the third region, and forming a second transistor of the second conductivity type in the fourth region.

摘要翻译： 一种制造半导体器件的方法包括：形成第一隔离绝缘膜和第二隔离绝缘膜，以限定第一，第二，第三和第四区域，形成第一绝缘膜，通过第一和第二区域注入第一导电类型的第一杂质; 在第一深度处将第一，第二和第四区域的绝缘膜形成为比第一绝缘膜更薄的第二绝缘膜，在第二绝缘膜中将第二导电类型的第二杂质通过第二绝缘膜注入第三区域 深度在所述半导体衬底中，在比所述第二深度浅的第三深度处将第二导电类型的第三杂质注入所述第三区域，在所述第三区域中形成所述第一导电类型的第一晶体管，以及形成所述第二晶体管， 第四区域的第二导电类型。

公开(公告)号：US08216895B2

公开(公告)日：2012-07-10

申请号：US12833279

申请日：2010-07-09

申请人： Akihiro Usujima ,  Shigeo Satoh

发明人： Akihiro Usujima ,  Shigeo Satoh

IPC分类号： H01L21/8238

CPC分类号： H01L21/823892 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823807 ,  H01L21/823878

摘要： A method of manufacturing a semiconductor device includes forming a first and a second isolation insulating film to define a first, a second, a third and a fourth region, forming a first insulating film, implanting a first impurity of a first conductivity type through the first insulating film into the first, the second and the fourth region at a first depth, forming a second insulating film thinner than the first insulating film, implanting a second impurity of a second conductivity type through the second insulating film into the third region at a second depth in the semiconductor substrate, implanting a third impurity of the second conductivity type into the third region at a third depth shallower than the second depth, forming a first transistor of the first conductivity type in the third region, and forming a second transistor of the second conductivity type in the fourth region.

摘要翻译： 一种制造半导体器件的方法包括：形成第一隔离绝缘膜和第二隔离绝缘膜，以限定第一，第二，第三和第四区域，形成第一绝缘膜，通过第一和第二区域注入第一导电类型的第一杂质; 在第一深度处将第一，第二和第四区域的绝缘膜形成为比第一绝缘膜更薄的第二绝缘膜，在第二绝缘膜中将第二导电类型的第二杂质通过第二绝缘膜注入第三区域 深度在所述半导体衬底中，在比所述第二深度浅的第三深度处将第二导电类型的第三杂质注入所述第三区域，在所述第三区域中形成所述第一导电类型的第一晶体管，以及形成所述第二晶体管， 第四区域的第二导电类型。

公开(公告)号：US08470656B2

公开(公告)日：2013-06-25

申请号：US13544376

申请日：2012-07-09

申请人： Akihiro Usujima ,  Shigeo Satoh

发明人： Akihiro Usujima ,  Shigeo Satoh

IPC分类号： H01L21/76

CPC分类号： H01L21/823418 ,  H01L21/823468

摘要： A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area.

摘要翻译： 一种半导体器件包括：第一晶体管，包括第一源极/漏极区域和第一侧壁间隔物;以及第二晶体管，包括第二源极/漏极区域和第二侧壁间隔物，第一侧壁间隔物具有第一宽度，第二侧壁间隔物 具有比第一宽度宽的第二宽度，并且第一源极/漏极区域具有第一区域，并且第二源极/漏极区域具有比第一区域大的第二区域。

公开(公告)号：US08237219B2

公开(公告)日：2012-08-07

申请号：US12877882

申请日：2010-09-08

申请人： Akihiro Usujima ,  Shigeo Satoh

发明人： Akihiro Usujima ,  Shigeo Satoh

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L21/336

CPC分类号： H01L21/823418 ,  H01L21/823468

摘要： A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area.

摘要翻译： 半导体器件包括：第一晶体管，包括第一源极/漏极区域和第一侧壁隔离物;以及第二晶体管，包括第二源极/漏极区域和第二侧壁间隔物，第一侧壁间隔物具有第一宽度，第二侧壁间隔物 具有比第一宽度宽的第二宽度，并且第一源极/漏极区域具有第一区域，并且第二源极/漏极区域具有比第一区域大的第二区域。

公开(公告)号：US20110018067A1

公开(公告)日：2011-01-27

申请号：US12833279

申请日：2010-07-09

申请人： Akihiro Usujima ,  Shigeo Satoh

发明人： Akihiro Usujima ,  Shigeo Satoh

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823892 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823807 ,  H01L21/823878

摘要： A method of manufacturing a semiconductor device includes forming a first and a second isolation insulating film to define a first, a second, a third and a fourth region, forming a first insulating film, implanting a first impurity of a first conductivity type through the first insulating film into the first, the second and the fourth region at a first depth, forming a second insulating film thinner than the first insulating film, implanting a second impurity of a second conductivity type through the second insulating film into the third region at a second depth in the semiconductor substrate, implanting a third impurity of the second conductivity type into the third region at a third depth shallower than the second depth, forming a first transistor of the first conductivity type in the third region, and forming a second transistor of the second conductivity type in the fourth region.

摘要翻译： 一种制造半导体器件的方法包括：形成第一隔离绝缘膜和第二隔离绝缘膜，以限定第一，第二，第三和第四区域，形成第一绝缘膜，通过第一和第二区域注入第一导电类型的第一杂质; 在第一深度处将第一，第二和第四区域的绝缘膜形成为比第一绝缘膜更薄的第二绝缘膜，在第二绝缘膜中将第二导电类型的第二杂质通过第二绝缘膜注入第三区域 深度在所述半导体衬底中，在比所述第二深度浅的第三深度处将第二导电类型的第三杂质注入所述第三区域，在所述第三区域中形成所述第一导电类型的第一晶体管，以及形成所述第二晶体管， 第四区域的第二导电类型。

公开(公告)号：US20090174009A1

公开(公告)日：2009-07-09

申请号：US12350227

申请日：2009-01-08

申请人： Akihiro Usujima ,  Hideyuki Kojima

发明人： Akihiro Usujima ,  Hideyuki Kojima

IPC分类号： H01L27/088 ,  H01L21/8232

CPC分类号： H01L21/823412 ,  H01L27/088

摘要： The semiconductor device includes the concentration of the impurity of the first conductivity type in a doped channel layer of a first conductivity type in the pass transistor is set at a relatively low value, and pocket regions of the first conductivity type in a pass transistor are formed so as to be relatively shallow with a relatively high impurity concentration.

摘要翻译： 半导体器件包括在传输晶体管中的第一导电类型的掺杂沟道层中的第一导电类型的杂质的浓度设定为相对较低的值，并且形成传输晶体管中的第一导电类型的穴区 以相对较浅的杂质浓度较高。

公开(公告)号：US20110156173A1

公开(公告)日：2011-06-30

申请号：US12958555

申请日：2010-12-02

申请人： Akihiro Usujima

发明人： Akihiro Usujima

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/0619 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835

摘要： A semiconductor device includes a first pocket region and a second pocket region. The source region includes a first extension region having a concentration peak located at a first depth from a surface of the semiconductor substrate, and the first pocket region has a concentration peak located deeper than the first depth, and the drain region includes a second extension region having a concentration peak located at a second depth from the surface of the semiconductor substrate, and the second pocket region has a concentration peak located shallower than the second depth.

摘要翻译： 半导体器件包括第一袋区和第二袋区。 源极区域包括具有位于距离半导体衬底的表面的第一深度处的浓度峰值的第一延伸区域，并且第一空穴区域具有位于比第一深度更深的浓度峰值，并且漏极区域包括第二延伸区域 具有位于距离半导体衬底的表面的第二深度处的浓度峰，并且第二袋区具有位于比第二深度浅的浓度峰。

公开(公告)号：US20100308420A1

公开(公告)日：2010-12-09

申请号：US12599431

申请日：2007-07-31

申请人： Akihiro Usujima ,  Junichi Ariyoshi ,  Taiji Ema

发明人： Akihiro Usujima ,  Junichi Ariyoshi ,  Taiji Ema

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/11526 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823468 ,  H01L27/105 ,  H01L27/11546 ,  H01L29/40114 ,  H01L29/7881

摘要： A semiconductor device includes a memory transistor including a first side wall insulating film and a second side wall insulating film disposed on the outside; a high-voltage transistor including a third side wall insulating film having the same composition as that of the first side wall insulating film, and a fourth side wall insulating film having the same composition as that of the second side wall insulating film, the fourth side wall insulating film being disposed on the outside; and a low-voltage transistor including a fifth side wall insulating film having the same composition as that of the second and fourth side wall insulating films. The memory transistor, the high-voltage transistor, and the low-voltage transistor are disposed on the same substrate. A total side wall spacer width of the low-voltage transistor is smaller than that of the high-voltage transistor by a thickness corresponding to the third side wall insulating film.

摘要翻译： 半导体器件包括存储晶体管，其包括设置在外部的第一侧壁绝缘膜和第二侧壁绝缘膜; 包括具有与第一侧壁绝缘膜相同组成的第三侧壁绝缘膜的高压晶体管，以及具有与第二侧壁绝缘膜相同组成的第四侧壁绝缘膜，第四侧 壁绝缘膜设置在外部; 以及包括具有与第二和第四侧壁绝缘膜相同组成的第五侧壁绝缘膜的低压晶体管。 存储晶体管，高压晶体管和低压晶体管设置在同一基板上。 低压晶体管的总侧壁间隔物宽度小于高压晶体管的相对于第三侧壁绝缘膜的厚度。

公开(公告)号：US08637938B2

公开(公告)日：2014-01-28

申请号：US12958555

申请日：2010-12-02

申请人： Akihiro Usujima

发明人： Akihiro Usujima

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/0619 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835

摘要： A semiconductor device includes a first pocket region and a second pocket region. The source region includes a first extension region having a concentration peak located at a first depth from a surface of the semiconductor substrate, and the first pocket region has a concentration peak located deeper than the first depth, and the drain region includes a second extension region having a concentration peak located at a second depth from the surface of the semiconductor substrate, and the second pocket region has a concentration peak located shallower than the second depth.

摘要翻译： 半导体器件包括第一袋区域和第二袋区域。 源极区域包括具有位于距离半导体衬底的表面的第一深度处的浓度峰值的第一延伸区域，并且第一空穴区域具有位于比第一深度更深的浓度峰值，并且漏极区域包括第二延伸区域 具有位于距离半导体衬底的表面的第二深度处的浓度峰，并且第二袋区具有位于比第二深度浅的浓度峰。

公开(公告)号：US06586264B2

公开(公告)日：2003-07-01

申请号：US09940660

申请日：2001-08-29

申请人： Akihiro Usujima

发明人： Akihiro Usujima

IPC分类号： G01R3126

CPC分类号： G06F17/5018

摘要： For a semiconductor device including a gate electrode in an area of part of a surface of a semiconductor substrate, a gate length is determined and to be set as an upper-limit gate length. For a semiconductor device of which a gate length is almost equal to the upper-limit gate length, an impurity implantation condition is determined to calculate a representative impurity concentration distribution. A limit gate length is obtained according to the representative impurity concentration distribution. For a semiconductor device of which a gate length is equal to or greater than the limit gate length and equal to or less than the upper-limit gate length, an impurity concentration distribution of the semiconductor device is calculated according to the representative impurity concentration distribution. Characteristics of the semiconductor device are obtained according to the impurity concentration distribution. This method reduces the period of time to calculate the characteristics of the semiconductor device.