公开(公告)号：US08470656B2

公开(公告)日：2013-06-25

申请号：US13544376

申请日：2012-07-09

申请人： Akihiro Usujima ,  Shigeo Satoh

发明人： Akihiro Usujima ,  Shigeo Satoh

IPC分类号： H01L21/76

CPC分类号： H01L21/823418 ,  H01L21/823468

摘要： A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area.

摘要翻译： 一种半导体器件包括：第一晶体管，包括第一源极/漏极区域和第一侧壁间隔物;以及第二晶体管，包括第二源极/漏极区域和第二侧壁间隔物，第一侧壁间隔物具有第一宽度，第二侧壁间隔物 具有比第一宽度宽的第二宽度，并且第一源极/漏极区域具有第一区域，并且第二源极/漏极区域具有比第一区域大的第二区域。

公开(公告)号：US20120319182A1

公开(公告)日：2012-12-20

申请号：US13447808

申请日：2012-04-16

申请人： Shigeo Satoh ,  Takae Sukegawa

发明人： Shigeo Satoh ,  Takae Sukegawa

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66689 ,  H01L29/7816

摘要： A semiconductor device production method includes: forming in a silicon substrate first and second region of first and second conductivity type in contact with each other; forming a gate electrode above the first and the second region; forming an insulation film covering part of the gate electrode and part of the second region; forming a source region and a drain region of the second conductivity type; forming interlayer insulation film covering the gate electrode and the insulation film; and forming in the interlayer insulation film first, second and third contact hole reaching the source region, the drain region, and the gate electrode, respectively, and at least one additional hole reaching the insulation film, and forming a conductive film in the first, the second, and the third contact hole and the additional hole to form first, second and third electrically conductive via and electrically conductive member.

摘要翻译： 半导体器件制造方法包括：在硅衬底中形成彼此接触的第一和第二导电类型的第一和第二区域; 在第一和第二区域之上形成栅电极; 形成覆盖所述栅电极的一部分和所述第二区的一部分的绝缘膜; 形成第二导电类型的源区和漏区; 覆盖栅电极和绝缘膜的层间绝缘膜; 并且分别在层间绝缘膜中形成第一，第二和第三接触孔，分别到达源极区域，漏极区域和栅极电极，以及至少一个到达绝缘膜的附加孔，并且在第一， 第二和第三接触孔和附加孔，以形成第一，第二和第三导电通孔和导电构件。

公开(公告)号：US20120091534A1

公开(公告)日：2012-04-19

申请号：US13329606

申请日：2011-12-19

申请人： Shigeo Satoh

发明人： Shigeo Satoh

IPC分类号： H01L27/092

CPC分类号： H01L29/7843 ,  H01L21/31155 ,  H01L21/823807 ,  H01L21/823828 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed above the semiconductor substrate, traversing the p-MOS active region and defining a p-MOS channel region under the p-MOS gate electrode structure; a compressive stress film selectively formed above the p-MOS active region and covering the p-MOS gate electrode structure; and a stress released region selectively formed above the element isolation region in the p-MOS region and releasing stress in the compressive stress film, wherein a compressive stress along the gate length direction and a tensile stress along the gate width direction are exerted on the p-MOS channel region. The performance of the semiconductor device can be improved by controlling the stress separately for the active region and element isolation region.

摘要翻译： 半导体器件包括：具有p-MOS区的半导体衬底; 形成在所述半导体衬底的表面部分并限定所述p-MOS区中的p-MOS有源区的元件隔离区; 形成在半导体衬底上方的p-MOS栅极电极结构，穿过p-MOS有源区并在p-MOS栅电极结构下限定p-MOS沟道区; 选择性地形成在p-MOS有源区上方并覆盖p-MOS栅电极结构的压应力膜; 以及选择性地形成在p-MOS区域中的元件隔离区域上方并且释放压缩应力膜中的应力的应力释放区域，其中沿着栅极长度方向的压缩应力和沿着栅极宽度方向的拉伸应力施加在p -MOS通道区域。 通过分别对有源区域和元件隔离区域进行控制来提高半导体器件的性能。

公开(公告)号：US08102030B2

公开(公告)日：2012-01-24

申请号：US12754898

申请日：2010-04-06

申请人： Shigeo Satoh

发明人： Shigeo Satoh

IPC分类号： H01L27/088 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238

CPC分类号： H01L29/7843 ,  H01L21/31155 ,  H01L21/823807 ,  H01L21/823828 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed above the semiconductor substrate, traversing the p-MOS active region and defining a p-MOS channel region under the p-MOS gate electrode structure; a compressive stress film selectively formed above the p-MOS active region and covering the p-MOS gate electrode structure; and a stress released region selectively formed above the element isolation region in the p-MOS region and releasing stress in the compressive stress film, wherein a compressive stress along the gate length direction and a tensile stress along the gate width direction are exerted on the p-MOS channel region. The performance of the semiconductor device can be improved by controlling the stress separately for the active region and element isolation region.

摘要翻译： 半导体器件包括：具有p-MOS区的半导体衬底; 形成在所述半导体衬底的表面部分并限定所述p-MOS区中的p-MOS有源区的元件隔离区; 形成在半导体衬底上方的p-MOS栅极电极结构，穿过p-MOS有源区并在p-MOS栅电极结构下限定p-MOS沟道区; 选择性地形成在p-MOS有源区上方并覆盖p-MOS栅电极结构的压应力膜; 以及选择性地形成在p-MOS区域中的元件隔离区域上方并且释放压缩应力膜中的应力的应力释放区域，其中沿着栅极长度方向的压缩应力和沿着栅极宽度方向的拉伸应力施加在p -MOS通道区域。 通过分别对有源区域和元件隔离区域进行控制来提高半导体器件的性能。

公开(公告)号：US20110057253A1

公开(公告)日：2011-03-10

申请号：US12877882

申请日：2010-09-08

申请人： Akihiro USUJIMA ,  Shigeo SATOH

发明人： Akihiro USUJIMA ,  Shigeo SATOH

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L21/336

CPC分类号： H01L21/823418 ,  H01L21/823468

摘要： A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area.

摘要翻译： 半导体器件包括：第一晶体管，包括第一源极/漏极区域和第一侧壁隔离物;以及第二晶体管，包括第二源极/漏极区域和第二侧壁间隔物，第一侧壁间隔物具有第一宽度，第二侧壁间隔物 具有比第一宽度宽的第二宽度，并且第一源极/漏极区域具有第一区域，并且第二源极/漏极区域具有比第一区域大的第二区域。

公开(公告)号：US20100144117A1

公开(公告)日：2010-06-10

申请号：US12708519

申请日：2010-02-18

申请人： Sadahiro Kishii ,  Hirofumi Watatani ,  Masanori Terahara ,  Ryo Tanabe ,  Kaina Suzuki ,  Shigeo Satoh

发明人： Sadahiro Kishii ,  Hirofumi Watatani ,  Masanori Terahara ,  Ryo Tanabe ,  Kaina Suzuki ,  Shigeo Satoh

IPC分类号： H01L21/762

CPC分类号： H01L29/045 ,  H01L21/76232 ,  H01L29/7846

摘要： A trench is formed in a surface layer of a semiconductor substrate, the trench surrounding an active region. A lower insulating film made of insulating material is deposited over the semiconductor device, the lower insulating film filling a lower region of the trench and leaving an empty space in an upper region. An upper insulating film made of insulating material having therein a tensile stress is deposited on the lower insulating film, the upper insulating film filling the empty space left in the upper space. The upper insulating film and the lower insulating film deposited over the semiconductor substrate other than in the trench are removed.

摘要翻译： 沟槽形成在半导体衬底的表面层中，沟槽围绕有源区。 在半导体器件上沉积由绝缘材料制成的下绝缘膜，下绝缘膜填充沟槽的下部区域并在上部区域留下空的空间。 在其上具有拉伸应力的由绝缘材料制成的上绝缘膜沉积在下绝缘膜上，上绝缘膜填充留在上部空间中的空白空间。 去除沉积在半导体衬底上而不是在沟槽中的上绝缘膜和下绝缘膜。

公开(公告)号：US07354817B2

公开(公告)日：2008-04-08

申请号：US11300274

申请日：2005-12-15

申请人： Taketo Watanabe ,  Toshio Nomura ,  Shinichi Kawai ,  Takayuki Kawamata ,  Shigeo Satoh

发明人： Taketo Watanabe ,  Toshio Nomura ,  Shinichi Kawai ,  Takayuki Kawamata ,  Shigeo Satoh

IPC分类号： H01L21/8238

CPC分类号： H01L29/66537 ,  H01L21/823807 ,  H01L29/1041 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/7827 ,  H01L29/7833

摘要： A semiconductor device includes a semiconductor substrate. A gate electrode is formed on the semiconductor substrate via a gate insulating film. A source region and a drain region of a first conductivity type are formed on the first side and the second side of the gate electrode, respectively, in the semiconductor substrate. A punch-through stopper region of a second conductivity type is formed in the semiconductor substrate such that the second conductivity type punch-through stopper region is located between the source region and the drain region at distances from the source region and the drain region and extends in the direction perpendicular to the principal surface of the semiconductor substrate. The concentration of an impurity element of the second conductivity type in the punch-through stopper region is set to be at least five times the substrate impurity concentration between the source region and the drain region.

摘要翻译： 半导体器件包括半导体衬底。 栅电极通过栅极绝缘膜形成在半导体衬底上。 在半导体衬底中分别在栅电极的第一侧和第二侧上形成第一导电类型的源极区和漏极区。 第二导电类型的穿通止挡区形成在半导体衬底中，使得第二导电类型穿通阻止区位于距源极区和漏极区的距离处的源极区和漏极区之间，并延伸 在垂直于半导体衬底的主表面的方向上。 穿通阻止区域中的第二导电类型的杂质元素的浓度被设定为源极区域和漏极区域之间的衬底杂质浓度的至少五倍。

公开(公告)号：US20050285137A1

公开(公告)日：2005-12-29

申请号：US10970160

申请日：2004-10-22

申请人： Shigeo Satoh

发明人： Shigeo Satoh

IPC分类号： H01L21/3115 ,  H01L21/8238 ,  H01L29/73

CPC分类号： H01L29/7843 ,  H01L21/31155 ,  H01L21/823807 ,  H01L21/823828 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed above the semiconductor substrate, traversing the p-MOS active region and defining a p-MOS channel region under the p-MOS gate electrode structure; a compressive stress film selectively formed above the p-MOS active region and covering the p-MOS gate electrode structure; and a stress released region selectively formed above the element isolation region in the p-MOS region and releasing stress in the compressive stress film, wherein a compressive stress along the gate length direction and a tensile stress along the gate width direction are exerted on the p-MOS channel region. The performance of the semiconductor device can be improved by controlling the stress separately for the active region and element isolation region.

摘要翻译： 半导体器件包括：具有p-MOS区的半导体衬底; 形成在所述半导体衬底的表面部分并限定所述p-MOS区中的p-MOS有源区的元件隔离区; 形成在半导体衬底上方的p-MOS栅极电极结构，穿过p-MOS有源区并在p-MOS栅电极结构下限定p-MOS沟道区; 选择性地形成在p-MOS有源区上方并覆盖p-MOS栅电极结构的压应力膜; 以及选择性地形成在p-MOS区域中的元件隔离区域上方并且释放压缩应力膜中的应力的应力释放区域，其中沿着栅极长度方向的压缩应力和沿着栅极宽度方向的拉伸应力施加在p -MOS通道区域。 通过分别对有源区域和元件隔离区域进行控制来提高半导体器件的性能。

公开(公告)号：US08338919B2

公开(公告)日：2012-12-25

申请号：US13329606

申请日：2011-12-19

申请人： Shigeo Satoh

发明人： Shigeo Satoh

IPC分类号： H01L27/088 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238

CPC分类号： H01L29/7843 ,  H01L21/31155 ,  H01L21/823807 ,  H01L21/823828 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed above the semiconductor substrate, traversing the p-MOS active region and defining a p-MOS channel region under the p-MOS gate electrode structure; a compressive stress film selectively formed above the p-MOS active region and covering the p-MOS gate electrode structure; and a stress released region selectively formed above the element isolation region in the p-MOS region and releasing stress in the compressive stress film, wherein a compressive stress along the gate length direction and a tensile stress along the gate width direction are exerted on the p-MOS channel region. The performance of the semiconductor device can be improved by controlling the stress separately for the active region and element isolation region.

公开(公告)号：US08237219B2

公开(公告)日：2012-08-07

申请号：US12877882

申请日：2010-09-08

申请人： Akihiro Usujima ,  Shigeo Satoh

发明人： Akihiro Usujima ,  Shigeo Satoh

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L21/336

CPC分类号： H01L21/823418 ,  H01L21/823468

摘要： A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area.

摘要翻译： 半导体器件包括：第一晶体管，包括第一源极/漏极区域和第一侧壁隔离物;以及第二晶体管，包括第二源极/漏极区域和第二侧壁间隔物，第一侧壁间隔物具有第一宽度，第二侧壁间隔物 具有比第一宽度宽的第二宽度，并且第一源极/漏极区域具有第一区域，并且第二源极/漏极区域具有比第一区域大的第二区域。