公开(公告)号：USD363714S

公开(公告)日：1995-10-31

申请号：US27038

申请日：1994-08-11

申请人： Akira Onoda ,  Norihiko Shimose ,  Mitsunari Fujii ,  Yusuke Morita

设计人： Akira Onoda ,  Norihiko Shimose ,  Mitsunari Fujii ,  Yusuke Morita

公开(公告)号：US08643117B2

公开(公告)日：2014-02-04

申请号：US13145108

申请日：2010-01-18

申请人： Ryuta Tsuchiya ,  Nobuyuki Sugii ,  Yusuke Morita ,  Hiroyuki Yoshimoto ,  Takashi Ishigaki ,  Shinichiro Kimura

发明人： Ryuta Tsuchiya ,  Nobuyuki Sugii ,  Yusuke Morita ,  Hiroyuki Yoshimoto ,  Takashi Ishigaki ,  Shinichiro Kimura

IPC分类号： H01L21/70

CPC分类号： H01L21/84 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/78648

摘要： In an SOI-MISFET that operates with low power consumption at a high speed, an element area is reduced. While a diffusion layer region of an N-conductivity type MISFET region of the SOI type MISFET and a diffusion layer region of a P-conductivity type MISFET region of the SOI type MISFET are formed as a common region, well diffusion layers that apply substrate potentials to the N-conductivity type MISFET region and the P-conductivity type MISFET region are separated from each other by an STI layer. The diffusion layer regions that are located in the N- and P-conductivity type MISFET regions) and serve as an output portion of a CMISFET are formed as a common region and directly connected by silicified metal so that the element area is reduced.

摘要翻译： 在以高功率低功耗工作的SOI-MISFET中，元件面积减小。 虽然SOI型MISFET的N导电型MISFET区域的扩散层区域和SOI型MISFET的P导电型MISFET区域的扩散层区域形成为公共区域，但是施加衬底电位的阱扩散层 通过STI层将N导电型MISFET区域和P导电型MISFET区域相互分离。 位于N和P导电型MISFET区域中的扩散层区域）作为CMISFET的输出部分形成为公共区域，并通过硅化金属直接连接，使元件面积减小。

公开(公告)号：US20130041117A1

公开(公告)日：2013-02-14

申请号：US13639668

申请日：2011-04-04

申请人： Masahiro Hayashida ,  Hisaaki Yoshimura ,  Daisuke Nonaka ,  Yusuke Morita ,  Mitsuhiro Matsuo

发明人： Masahiro Hayashida ,  Hisaaki Yoshimura ,  Daisuke Nonaka ,  Yusuke Morita ,  Mitsuhiro Matsuo

IPC分类号： B01J19/18 ,  C08F20/14 ,  C08F2/01

CPC分类号： C08F2/01 ,  B01J19/0066 ,  B01J19/1806 ,  B01J19/242 ,  B01J2219/0004 ,  B01J2219/00094 ,  C08F2/001 ,  C08F220/18

摘要： Disclosed is an apparatus for producing a high-quality methacrylic polymer with good productivity, comprising a complete mixing type reactor 11, tubular reactors 12 and 13 which have been serially connected, and a volatile removing instrument 14, wherein at least two of the tubular reactors 12 and 13 are connected via a cooler 15 for cooling the reaction mixture. It is preferable that the cooler 15 is a multitubular cooler and the tubular reactors 12 and 13 are plug flow reactors.

摘要翻译： 公开了一种用于生产高质量甲基丙烯酸聚合物的装置，其具有良好的生产率，包括已经串联连接的完全混合型反应器11，管状反应器12和13以及挥发性去除装置14，其中至少两个管式反应器 12和13通过冷却器15连接，用于冷却反应混合物。 优选地，冷却器15是多管冷却器，并且管式反应器12和13是活塞流反应器。

公开(公告)号：US08034696B2

公开(公告)日：2011-10-11

申请号：US11802048

申请日：2007-05-18

申请人： Ryuta Tsuchiya ,  Yoshinobu Kimura ,  Yusuke Morita

发明人： Ryuta Tsuchiya ,  Yoshinobu Kimura ,  Yusuke Morita

IPC分类号： H01L21/20

CPC分类号： C30B23/00 ,  C30B25/00

摘要： It is an object of the present invention to provide a method of manufacturing an SOI wafer at low cost and with high yield. It is another object of the present invention to provide a semiconductor device including also bulk type MISFETs used as high voltage regions and a method of manufacturing the same without using complicated processes and increasing the size of a semiconductor chip.The method of manufacturing a semiconductor device comprises selectively epitaxially growing a single-crystal Si layer and continuously performing the epitaxial growth without bringing a substrate temperature increased during the growth to room temperature even once. An epitaxially grown surface is then etched and planarized. The substrate temperature is then cooled down to the room temperature.

摘要翻译： 本发明的目的是提供一种以低成本和高产率制造SOI晶片的方法。 本发明的另一个目的是提供一种半导体器件，其还包括用作高电压区域的体型型MISFET及其制造方法，而不需要使用复杂的工艺并增加半导体芯片的尺寸。 制造半导体器件的方法包括选择性地外延生长单晶Si层并连续进行外延生长，而不会使基板温度在生长至室温期间增加甚至一次。 然后将外延生长的表面蚀刻并平坦化。 然后将衬底温度冷却至室温。

公开(公告)号：US20090096036A1

公开(公告)日：2009-04-16

申请号：US12248250

申请日：2008-10-09

申请人： Takashi ISHIGAKI ,  Ryuta Tsuchiya ,  Yusuke Morita ,  Nobuyuki Sugii ,  Shinichiro Kimura ,  Toshiaki Iwamatsu

发明人： Takashi ISHIGAKI ,  Ryuta Tsuchiya ,  Yusuke Morita ,  Nobuyuki Sugii ,  Shinichiro Kimura ,  Toshiaki Iwamatsu

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L21/84 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/76283 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/1203 ,  H01L27/1207

摘要： There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. A the first elevated layer is thicker than the elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided.

摘要翻译： 提供了SOI-MISFET，其包括：SOI层; 设置在插入栅极绝缘体的SOI层上的栅电极; 以及第一升高层，其在SOI层上的栅电极的两个侧壁侧的SOI层高于栅电极，从而构成源极和漏极。 此外，还提供了一种体MISFET，包括：设置在硅衬底上的栅电极，其插入比SOI MISFET的栅极绝缘体更厚的栅极绝缘体; 以及构造在栅电极的两个侧壁处设置在半导体衬底上的源极和漏极的第二升高层。 第一升高层比升高的层厚，并且整个栅电极，SOI-MISFET的源极和漏极的一部分以及体MISFET的源极和漏极的一部分被硅化。

公开(公告)号：USD362849S

公开(公告)日：1995-10-03

申请号：US29065

申请日：1994-09-28

申请人： Toru Higashibata ,  Eiichiro Naito ,  Yusuke Morita

设计人： Toru Higashibata ,  Eiichiro Naito ,  Yusuke Morita

公开(公告)号：USD335664S

公开(公告)日：1993-05-18

申请号：US639177

申请日：1991-01-08

申请人： Yusuke Morita ,  Hiroaki Nishiyori

设计人： Yusuke Morita ,  Hiroaki Nishiyori

公开(公告)号：US08350328B2

公开(公告)日：2013-01-08

申请号：US12759559

申请日：2010-04-13

申请人： Takashi Ishigaki ,  Ryuta Tsuchiya ,  Yusuke Morita ,  Nobuyuki Sugii

发明人： Takashi Ishigaki ,  Ryuta Tsuchiya ,  Yusuke Morita ,  Nobuyuki Sugii

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： Characteristics of a semiconductor device having a FINFET are improved. The FINFET has: a channel layer arranged in an arch shape on a semiconductor substrate and formed of monocrystalline silicon; a front gate electrode formed on a part of an outside of the channel layer through a front gate insulating film; and a back gate electrode formed so as to be buried inside the channel layer through a back gate insulating film. The back gate electrode arranged inside the arch shape is arranged so as to pass through the front gate electrode.

摘要翻译： 具有FINFET的半导体器件的特性得到改善。 FINFET具有：在半导体衬底上以拱形形式布置并由单晶硅形成的沟道层; 前栅电极，其通过前栅极绝缘膜形成在沟道层的外部的一部分上; 以及形成为通过背栅绝缘膜埋设在沟道层内的背栅电极。 布置在拱形内侧的背栅极布置成穿过前栅电极。

公开(公告)号：US20120249930A1

公开(公告)日：2012-10-04

申请号：US13425779

申请日：2012-03-21

申请人： Keisuke Takano ,  Takashi Sasabayashi ,  Arihiro Takeda ,  Keiji Tago ,  Jin Hirosawa ,  Hitomi Hasegawa ,  Yusuke Morita ,  Hirokazu Morimoto

发明人： Keisuke Takano ,  Takashi Sasabayashi ,  Arihiro Takeda ,  Keiji Tago ,  Jin Hirosawa ,  Hitomi Hasegawa ,  Yusuke Morita ,  Hirokazu Morimoto

IPC分类号： G02F1/1335

CPC分类号： G02F1/133526 ,  G02B27/2214 ,  G02F1/133707 ,  G02F1/134363 ,  G02F2001/13373

摘要： In one embodiment, a liquid crystal display device includes a lens array unit having a cylindrical lens array constituted by a plurality of cylindrical lenses each having a lens surface and a generatrix corresponding to the lens surface. The lens surface is arranged in a line in a direction orthogonally crossing the generatrix. A first substrate is arranged at a back side of the lens array unit and includes a pixel electrode in a belt shape extending in a different direction from the direction in which the generatrix extends. The pixel electrode is formed in a V character shape. A second substrate is arranged between the lens array unit and the first substrate including a counter electrode in a belt shape commonly arranged on the pixel electrodes extending in a parallel direction to the pixel electrode.

摘要翻译： 在一个实施例中，液晶显示装置包括透镜阵列单元，该透镜阵列单元具有由多个圆柱透镜构成的柱面透镜阵列，每个柱面透镜具有透镜表面和与透镜表面对应的母线。 透镜表面沿垂直于母线的方向排列成一行。 第一基板布置在透镜阵列单元的后侧，并且包括沿与母线延伸的方向不同的方向延伸的带状的像素电极。 像素电极形成为V字形。 第二基板布置在透镜阵列单元和第一基板之间，包括通常布置在沿像素电极的平行方向延伸的像素电极上的带状对置电极。

公开(公告)号：US08183115B2

公开(公告)日：2012-05-22

申请号：US13088020

申请日：2011-04-15

申请人： Takashi Ishigaki ,  Ryuta Tsuchiya ,  Yusuke Morita ,  Nobuyuki Sugii ,  Shinichiro Kimura ,  Toshiaki Iwamatsu

发明人： Takashi Ishigaki ,  Ryuta Tsuchiya ,  Yusuke Morita ,  Nobuyuki Sugii ,  Shinichiro Kimura ,  Toshiaki Iwamatsu

IPC分类号： H01L21/8234

CPC分类号： H01L21/84 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/76283 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/1203 ,  H01L27/1207

摘要： There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. The first elevated layer is thicker than the second elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided.

摘要翻译： 提供了SOI-MISFET，其包括：SOI层; 设置在插入栅极绝缘体的SOI层上的栅电极; 以及第一升高层，其在SOI层上的栅电极的两个侧壁侧的SOI层高于栅电极，从而构成源极和漏极。 此外，还提供了一种体MISFET，包括：设置在硅衬底上的栅电极，其插入比SOI MISFET的栅极绝缘体更厚的栅极绝缘体; 以及构造在所述栅电极的两个侧壁处设置在半导体衬底上的源极和漏极的第二升高层。 第一升高层比第二升高层厚，并且整个栅电极，SOI-MISFET的源极和漏极的一部分以及体MISFET的源极和漏极的一部分被硅化。