公开(公告)号：US06998225B2

公开(公告)日：2006-02-14

申请号：US10409079

申请日：2003-04-09

申请人： Akiyoshi Kudo ,  Hiroshi Kobayashi ,  Takanori Matsumoto

发明人： Akiyoshi Kudo ,  Hiroshi Kobayashi ,  Takanori Matsumoto

IPC分类号： G03F7/00 ,  G03F7/42

CPC分类号： H01L29/66863 ,  G03F7/425 ,  H01L21/28575 ,  H01L29/42316 ,  H01L29/66318 ,  H01L29/66462

摘要： A method of producing a compound semiconductor device using a lift-off process. The lift-off process includes forming a resist mask having an electrode opening on an active layer of a compound semiconductor that is on a substrate of a compound semiconductor; forming a metal layer on the resist mask and the active layer in the electrode opening; and dissolving the resist mask and removing the metal layer on the resist mask, leaving the metal layer on the active layer in the electrode opening as an electrode. The resist mask is removed sufficiently by using a resist remover consisting essentially of at least one compound selected from an amine-including compound and nitrogen-including cyclic compounds so that the residual resist mask need not be removed by ashing.

摘要翻译： 一种使用剥离工艺制造化合物半导体器件的方法。 剥离工艺包括在化合物半导体的衬底上的化合物半导体的有源层上形成具有电极开口的抗蚀剂掩模; 在抗蚀剂掩模和电极开口中的有源层上形成金属层; 并将抗蚀剂掩模溶解并除去抗蚀剂掩模上的金属层，将金属层留在电极开口中的有源层上作为电极。 通过使用基本上由至少一种选自含胺化合物和含氮环状化合物的化合物组成的抗蚀剂去除剂，足以去除抗蚀剂掩模，使得残余抗蚀剂掩模不需要通过灰化除去。

公开(公告)号：US06653667B2

公开(公告)日：2003-11-25

申请号：US10186614

申请日：2002-07-02

申请人： Akiyoshi Kudo

发明人： Akiyoshi Kudo

IPC分类号： H01L310328

CPC分类号： H01L29/8128

摘要： A GaAs-based semiconductor field-effect transistor in which electrons flowing from a source electrode to a drain electrode are controlled by a signal supplied to a gate electrode. The transistor includes an active layer made of a GaAs-based semiconductor material. A source electrode and a drain electrode are formed on the active layer. A gate electrode is formed on the active layer between the source electrode and the drain electrode. The thickness of an oxide layer of the GaAs-based semiconductor material on the active layer is approximately equal to the lattice constant of the GaAs-based semiconductor material. The thickness of the oxide layer is preferably about 4 through 6 Å, and, more preferably, about 5 Å.

摘要翻译： 其中从源电极向漏电极流动的电子通过提供给栅电极的信号来控制的GaAs基半导体场效应晶体管。 晶体管包括由GaAs基半导体材料制成的有源层。 源电极和漏电极形成在有源层上。 在源电极和漏电极之间的有源层上形成栅电极。 有源层上的GaAs基半导体材料的氧化物层的厚度近似等于GaAs基半导体材料的晶格常数。 氧化物层的厚度优选为约4至6埃，更优选为约5埃。

公开(公告)号：US20060281237A1

公开(公告)日：2006-12-14

申请号：US11382991

申请日：2006-05-12

申请人： Akiyoshi Kudo ,  Yoshiharu Anda ,  Akiyoshi Tamura

发明人： Akiyoshi Kudo ,  Yoshiharu Anda ,  Akiyoshi Tamura

IPC分类号： H01L21/338

CPC分类号： H01L29/207 ,  H01L29/66924 ,  H01L29/808

摘要： A method of manufacturing a junction field-effect transistor which controls variations of p-type impurities in a gate region and obtains a favorable PN junction characteristic includes: depositing ZnO in a thin layer by a sputtering method on a surface of a region in which a gate electrode of an n+-AlGaAs layer formed on a GaAs substrate is to be formed; forming a p-type gate region by solid-phase diffusion which is performed by processes of rapid heating and fast cooling; removing the ZnO with wet etching using tartaric acid and the like so as to expose the p-type gate region; and forming the gate electrode on the exposed p-type gate region.

摘要翻译： 一种控制栅极区域中的p型杂质的变化并获得良好的PN结特性的结型场效应晶体管的制造方法包括：在溅射法的薄层中，在 要形成在GaAs衬底上形成的n + + / - AlGaAs层的栅电极; 通过快速加热和快速冷却过程进行的固相扩散形成p型栅极区; 用酒石酸等湿法蚀刻除去ZnO，露出p型栅区; 以及在暴露的p型栅极区上形成栅电极。

公开(公告)号：US5801069A

公开(公告)日：1998-09-01

申请号：US594769

申请日：1996-01-31

申请人： Kenichi Harada ,  Takeshi Kuragaki ,  Osamu Ishihara ,  Kazuhiko Sato ,  Akiyoshi Kudo

发明人： Kenichi Harada ,  Takeshi Kuragaki ,  Osamu Ishihara ,  Kazuhiko Sato ,  Akiyoshi Kudo

IPC分类号： C30B33/10 ,  H01L21/00 ,  H01L21/302 ,  H01L21/3065 ,  H01L29/84 ,  H01L41/08 ,  H01L41/187 ,  H01L41/22 ,  H03H9/17

CPC分类号： H03H3/02 ,  H03H9/173 ,  H03H9/174 ,  H03H2003/021 ,  H03H2003/023

摘要： A method of fabricating a thin film piezoelectric device includes preparing a semiconductor substrate having a surface; forming an etch stopping layer having an etching rate on the surface of the semiconductor substrate; forming a first semiconductor layer having an etching rate higher than the etching rate of the etch stopping layer on the etch stopping layer; forming a first electrode on a region of the first semiconductor layer; forming a piezoelectric film on the first electrode; forming a second electrode on the piezoelectric film; and etching a portion of the first semiconductor layer where the first electrode, the piezoelectric film, and the second electrode overlap, from the surface of the first semiconductor layer, selectively with respect to the etch stopping layer, thereby forming a cavity in the first semiconductor layer. Even when a compound semiconductor is employed as the substrate, the etching forming a cavity is stopped at the etch stopping layer in the direction perpendicular to the surface of the first semiconductor layer so that a cavity having a uniform depth is produced with high controllability.

摘要翻译： 制造薄膜压电器件的方法包括制备具有表面的半导体衬底; 在所述半导体衬底的表面上形成具有蚀刻速率的蚀刻停止层; 形成蚀刻速率高于蚀刻停止层上的蚀刻停止层的蚀刻速率的第一半导体层; 在所述第一半导体层的区域上形成第一电极; 在所述第一电极上形成压电膜; 在所述压电膜上形成第二电极; 并且相对于蚀刻停止层选择性地从第一半导体层的表面蚀刻第一电极，压电膜和第二电极重叠的第一半导体层的一部分，从而在第一半导体中形成空腔 层。 即使当使用化合物半导体作为衬底时，形成空腔的蚀刻在垂直于第一半导体层的表面的方向上在蚀刻停止层处停止，从而产生具有高可控性的均匀深度的空腔。

公开(公告)号：US5530272A

公开(公告)日：1996-06-25

申请号：US329519

申请日：1994-10-26

申请人： Akiyoshi Kudo ,  Kazuo Hayashi

发明人： Akiyoshi Kudo ,  Kazuo Hayashi

IPC分类号： H01L29/812 ,  H01L21/335 ,  H01L21/338 ,  H01L29/06 ,  H01L29/778 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： B82Y10/00 ,  H01L29/66469 ,  H01L29/7783

摘要： A compound semiconductor device includes a carrier supply layer supplying free charge carriers and having high dopant impurity concentration regions with a prescribed width, disposed in stripe shapes along a main current flow direction, parallel to each other, and spaced at an interval, and a carrier channel layer to which free charge carriers are supplied from the carrier supply layer including an electron channel having a high free carrier density at portions corresponding to respective high dopant impurity concentration regions of the carrier supply layer in the vicinity of a heterojunction interface. The heterojunction interface formed by the carrier channel layer and the carrier supply layer has a periodic undulating shape with convex portions and valley portions in stripe shapes extending parallel to the main current flow direction. A pseudo one-dimensional electron channel is formed in the vicinity of the high dopant impurity concentration region of the carrier supply layer whereby electron mobility is increased. The regions other than the high dopant impurity concentration regions of the carrier supply layer have a low dopant impurity concentration whereby the charge carrier quantity and output per unit chip area are increased, thereby increasing power output without increasing chip area.

摘要翻译： 化合物半导体器件包括载体供给层，其供给自由电荷载体，并且具有规定宽度的高掺杂杂质浓度区域，沿主电流流动方向以条状形状彼此平行地设置并间隔开，并且载体 从载体供给层向载流子供给层供给包含自由载流子浓度高的电子通道的沟道层，在与异质结界面附近的载流子供给层的各个高掺杂剂杂质浓度区域对应的部分。 由载流子通道层和载流子供给层形成的异质结界面具有周期性起伏的形状，具有平行于主流动方向延伸的条状的凸部和谷部。 在载流子供给层的高掺杂剂杂质浓度区域附近形成伪一维电子通道，由此增加电子迁移率。 载流子供给层的高掺杂剂杂质浓度区域以外的区域具有低掺杂剂杂质浓度，由此每单位芯片面积的电荷载体量和输出增加，从而增加功率输出而不增加芯片面积。