Digital Signal Processor (DSP) Architecture For A Hybrid Television Tuner
    2.
    发明申请
    Digital Signal Processor (DSP) Architecture For A Hybrid Television Tuner 有权
    混合电视调谐器的数字信号处理器(DSP)架构

    公开(公告)号:US20100328536A1

    公开(公告)日:2010-12-30

    申请号:US12493955

    申请日:2009-06-29

    IPC分类号: H04N5/00 H04N5/50 H04N5/455

    摘要: According to one aspect, a mixed-signal tuner for analog and digital TV reception incorporates a demodulator for analog TV, employing various features for resolving limitations of the analog circuitry and for achieving compatibility with various global TV standards. Such features, which may be present in one or more embodiments, include the use of a variable sample rate in all digital clocks for frequency planning, and use of a microcontroller (MCU) to control various circuitry of the tuner.

    摘要翻译: 根据一个方面,用于模拟和数字电视接收的混合信号调谐器包括用于模拟电视的解调器,其采用各种特征来解决模拟电路的限制并实现与各种全球电视标准的兼容性。 可以存在于一个或多个实施例中的这些特征包括在用于频率规划的所有数字时钟中使用可变采样率,以及使用微控制器(MCU)来控制调谐器的各种电路。

    Digital signal processor (DSP) architecture for a hybrid television tuner
    3.
    发明授权
    Digital signal processor (DSP) architecture for a hybrid television tuner 有权
    用于混合电视调谐器的数字信号处理器(DSP)架构

    公开(公告)号:US08576343B2

    公开(公告)日:2013-11-05

    申请号:US12493955

    申请日:2009-06-29

    IPC分类号: H04N5/44

    摘要: According to one aspect, a mixed-signal tuner for analog and digital TV reception incorporates a demodulator for analog TV, employing various features for resolving limitations of the analog circuitry and for achieving compatibility with various global TV standards. Such features, which may be present in one or more embodiments, include the use of a variable sample rate in all digital clocks for frequency planning, and use of a microcontroller (MCU) to control various circuitry of the tuner.

    摘要翻译: 根据一个方面,用于模拟和数字电视接收的混合信号调谐器包括用于模拟电视的解调器,其采用各种特征来解决模拟电路的限制并实现与各种全球电视标准的兼容性。 可以存在于一个或多个实施例中的这些特征包括在用于频率规划的所有数字时钟中使用可变采样率,以及使用微控制器(MCU)来控制调谐器的各种电路。

    Providing image rejection calibration for a receiver
    5.
    发明授权
    Providing image rejection calibration for a receiver 有权
    为接收机提供镜像抑制校准

    公开(公告)号:US08265584B2

    公开(公告)日:2012-09-11

    申请号:US12493738

    申请日:2009-06-29

    IPC分类号: H04B1/10

    CPC分类号: H04B1/28

    摘要: According to one embodiment, a method for updating filter values of an image canceller is provided. The method may include determining a channel-to-image (C/I) ratio between a channel signal and an image signal at the canceller input and generating a gain control value based at least in part on the C/I ratio. Then correlations between the channel signal and the image signal at the canceller's input and output can be generated, along with a gear control value based at least in part on a ratio between the correlations. In turn, one or more filters of the canceller can be updated using the control values.

    摘要翻译: 根据一个实施例,提供了一种用于更新图像消除器的滤波器值的方法。 该方法可以包括确定在消除器输入处的通道信号和图像信号之间的通道到图像(C / I)比,并且至少部分地基于C / I比产生增益控制值。 然后,可以产生在消除器的输入和输出处的通道信号和图像信号之间的相关性,以及至少部分地基于相关性之间的比率的齿轮控制值。 反过来,可以使用控制值来更新消除器的一个或多个过滤器。

    Providing Image Rejection Calibration For A Receiver
    6.
    发明申请
    Providing Image Rejection Calibration For A Receiver 有权
    为接收机提供图像抑制校准

    公开(公告)号:US20100330947A1

    公开(公告)日:2010-12-30

    申请号:US12493738

    申请日:2009-06-29

    IPC分类号: H04B1/10

    CPC分类号: H04B1/28

    摘要: According to one embodiment, a method for updating filter values of an image canceller is provided. The method may include determining a channel-to-image (C/I) ratio between a channel signal and an image signal at the canceller input and generating a gain control value based at least in part on the C/I ratio. Then correlations between the channel signal and the image signal at the canceller's input and output can be generated, along with a gear control value based at least in part on a ratio between the correlations. In turn, one or more filters of the canceller can be updated using the control values.

    摘要翻译: 根据一个实施例,提供了一种用于更新图像消除器的滤波器值的方法。 该方法可以包括确定在消除器输入处的通道信号和图像信号之间的通道到图像(C / I)比,并且至少部分地基于C / I比产生增益控制值。 然后,可以产生在消除器的输入和输出处的通道信号和图像信号之间的相关性,以及至少部分地基于相关性之间的比率的齿轮控制值。 反过来,可以使用控制值来更新消除器的一个或多个过滤器。

    Controllable image cancellation in a radio receiver
    7.
    发明申请
    Controllable image cancellation in a radio receiver 有权
    无线电接收机中的可控图像消除

    公开(公告)号:US20100167680A1

    公开(公告)日:2010-07-01

    申请号:US12317786

    申请日:2008-12-30

    IPC分类号: H04B1/10

    CPC分类号: H04B1/28 H04B1/0032

    摘要: In one embodiment, a receiver includes parallel paths for signal channel processing and image channel processing. The paths may include a mixer to receive an intermediate frequency (IF) signal and to downconvert the IF signal to a channel baseband signal, a filter to generate a filtered channel value, a combiner to combine the channel baseband signal with a filtered channel value from the other path to obtain a channel path output, in addition to one or more controllers to generate a step control signal and update a weighting of the filters based at least in part on the step control signal.

    摘要翻译: 在一个实施例中,接收机包括用于信号信道处理和图像信道处理的并行路径。 路径可以包括用于接收中频(IF)信号并且将IF信号下变频到信道基带信号的混频器,用于产生经滤波的信道值的滤波器,组合器以将信道基带信号与滤波后的信道值 除了一个或多个控制器以至少部分地基于步进控制信号产生步进控制信号和更新滤波器的加权之外,获得通道路径输出的另一路径。

    System and method of changing a PWM power spectrum
    9.
    发明授权
    System and method of changing a PWM power spectrum 有权
    改变PWM功率谱的系统和方法

    公开(公告)号:US08154358B2

    公开(公告)日:2012-04-10

    申请号:US12729000

    申请日:2010-03-22

    IPC分类号: H03F3/38 H03K7/08

    摘要: In a particular embodiment, a circuit device includes a pulse edge control circuit to receive at least one pulse-width modulated (PWM) signal from a PWM source. The pulse edge control circuit is adapted to selectively invert and swap the at least one PWM signal with a logic-inverted duty-cycle complement of the at least one PWM signal at discrete time intervals to produce at least one modulated PWM signal having a changed power spectrum. The pulse edge control circuit provides the at least one modulated PWM signal to at least one output of the pulse edge control circuit.

    摘要翻译: 在特定实施例中,电路装置包括脉冲边缘控制电路,以从PWM源接收至少一个脉冲宽度调制(PWM)信号。 脉冲沿控制电路适于以离散时间间隔以至少一个PWM信号的逻辑反相占空比补码选择性地反转和交换至少一个PWM信号,以产生具有改变的功率的至少一个调制的PWM信号 光谱。 脉冲沿控制电路将至少一个调制的PWM信号提供给脉冲沿控制电路的至少一个输出端。

    Precise phase detector
    10.
    发明授权
    Precise phase detector 失效
    精确相位检测器

    公开(公告)号:US06768347B2

    公开(公告)日:2004-07-27

    申请号:US10145412

    申请日:2002-05-12

    IPC分类号: H03D900

    CPC分类号: H03D13/003

    摘要: A digital phase detector with a master stage having imbalanced latching devices with intentional input-referred offset for determining which one of a pair of input signals is leading the other and a slave stage connected to the master stage imbalanced latching devices and which slave stage is transparent when ones of the master state imbalanced latching devices are set to a logical one and which is latched and held when the master state latching devices are reset and armed for the next phase measurement.

    摘要翻译: 具有主级的数字相位检测器具有不平衡的锁存装置,其具有有意的输入参考偏移量,用于确定一对输入信号中的哪一个引导另一个,以及与主级不平衡闭锁装置连接的从动级,以及从属级是透明的 当主状态不平衡锁存装置中的一个被设置为逻辑锁存装置,并且当主状态锁存装置被复位并被布防用于下一相位测量时被锁存和保持。