公开(公告)号：US08576343B2

公开(公告)日：2013-11-05

申请号：US12493955

申请日：2009-06-29

申请人： Alan Hendrickson ,  David Trager ,  Mitch Reid ,  Li Gao ,  John Khoury

发明人： Alan Hendrickson ,  David Trager ,  Mitch Reid ,  Li Gao ,  John Khoury

IPC分类号： H04N5/44

CPC分类号： H04N5/46 ,  H03J1/0008 ,  H04N5/455 ,  H04N5/50 ,  H04N21/4263

摘要： According to one aspect, a mixed-signal tuner for analog and digital TV reception incorporates a demodulator for analog TV, employing various features for resolving limitations of the analog circuitry and for achieving compatibility with various global TV standards. Such features, which may be present in one or more embodiments, include the use of a variable sample rate in all digital clocks for frequency planning, and use of a microcontroller (MCU) to control various circuitry of the tuner.

摘要翻译： 根据一个方面，用于模拟和数字电视接收的混合信号调谐器包括用于模拟电视的解调器，其采用各种特征来解决模拟电路的限制并实现与各种全球电视标准的兼容性。 可以存在于一个或多个实施例中的这些特征包括在用于频率规划的所有数字时钟中使用可变采样率，以及使用微控制器（MCU）来控制调谐器的各种电路。

公开(公告)号：US20100328544A1

公开(公告)日：2010-12-30

申请号：US12603877

申请日：2009-10-22

申请人： Alan Hendrickson ,  David Trager ,  Mitch Reid ,  Li Gao ,  John Khoury

发明人： Alan Hendrickson ,  David Trager ,  Mitch Reid ,  Li Gao ,  John Khoury

IPC分类号： H04N5/455 ,  H04L27/08

CPC分类号： H04N5/46 ,  H03J1/0008 ,  H04N5/455 ,  H04N5/50 ,  H04N21/4263

摘要： According to one aspect, a mixed-signal tuner for analog and digital TV reception incorporates a demodulator for analog TV, employing various features for resolving limitations of the analog circuitry and for achieving compatibility with various global TV standards. Such features, which may be present in one or more embodiments, include the use of a variable sample rate in all digital clocks for frequency planning, and use of a microcontroller (MCU) to control various circuitry of the tuner.

公开(公告)号：US08599312B2

公开(公告)日：2013-12-03

申请号：US12603877

申请日：2009-10-22

申请人： Alan Hendrickson ,  David Trager ,  Mitch Reid ,  Li Gao ,  John Khoury

发明人： Alan Hendrickson ,  David Trager ,  Mitch Reid ,  Li Gao ,  John Khoury

IPC分类号： H04N3/27

CPC分类号： H04N5/46 ,  H03J1/0008 ,  H04N5/455 ,  H04N5/50 ,  H04N21/4263

摘要： According to one aspect, a mixed-signal tuner for analog and digital TV reception incorporates a demodulator for analog TV, employing various features for resolving limitations of the analog circuitry and for achieving compatibility with various global TV standards. Such features, which may be present in one or more embodiments, include the use of a variable sample rate in all digital clocks for frequency planning, and use of a microcontroller (MCU) to control various circuitry of the tuner.

公开(公告)号：US20100328536A1

公开(公告)日：2010-12-30

申请号：US12493955

申请日：2009-06-29

申请人： Alan Hendrickson ,  David Trager ,  Mitch Reid ,  Li Gao ,  John Khoury

发明人： Alan Hendrickson ,  David Trager ,  Mitch Reid ,  Li Gao ,  John Khoury

IPC分类号： H04N5/00 ,  H04N5/50 ,  H04N5/455

CPC分类号： H04N5/46 ,  H03J1/0008 ,  H04N5/455 ,  H04N5/50 ,  H04N21/4263

摘要： According to one aspect, a mixed-signal tuner for analog and digital TV reception incorporates a demodulator for analog TV, employing various features for resolving limitations of the analog circuitry and for achieving compatibility with various global TV standards. Such features, which may be present in one or more embodiments, include the use of a variable sample rate in all digital clocks for frequency planning, and use of a microcontroller (MCU) to control various circuitry of the tuner.

摘要翻译： 根据一个方面，用于模拟和数字电视接收的混合信号调谐器包括用于模拟电视的解调器，其采用各种特征来解决模拟电路的限制并实现与各种全球电视标准的兼容性。 可以存在于一个或多个实施例中的这些特征包括在用于频率规划的所有数字时钟中使用可变采样率，以及使用微控制器（MCU）来控制调谐器的各种电路。

公开(公告)号：US08593526B1

公开(公告)日：2013-11-26

申请号：US13586854

申请日：2012-08-15

申请人： Alan Hendrickson ,  David Trager ,  Zhongchun Liu

发明人： Alan Hendrickson ,  David Trager ,  Zhongchun Liu

IPC分类号： H04N17/02 ,  H04N5/08

CPC分类号： H04N5/213 ,  H04N5/21 ,  H04N17/045

摘要： Techniques are disclosed relating to video signal-to-noise ratio (VSNR) measurement. In one embodiment, an analog television signal receiver includes a measurement circuit configured to measure noise in a video signal over one or more intervals that correspond to a horizontal control signal of the video signal and a control unit configured to determine a VSNR based on the measurement. In another embodiment, a first noise calculation circuit is configured to determine first noise information from a video signal and a second noise calculation circuit is configured to determine second noise information from a video signal in a manner different from the first noise calculation circuit. A control unit may be configured to generate a VSNR based on one or both of the first noise information and the second noise information.

摘要翻译： 公开了与视频信噪比（VSNR）测量有关的技术。 在一个实施例中，模拟电视信号接收机包括测量电路，该测量电路经配置以在对应于视频信号的水平控制信号的一个或多个间隔上测量视频信号中的噪声;以及控制单元，被配置为基于测量来确定VSNR 。 在另一个实施例中，第一噪声计算电路被配置为从视频信号确定第一噪声信息，并且第二噪声计算电路被配置为以与第一噪声计算电路不同的方式从视频信号确定第二噪声信息。 控制单元可以被配置为基于第一噪声信息和第二噪声信息中的一个或两者来生成VSNR。

公开(公告)号：US08228431B2

公开(公告)日：2012-07-24

申请号：US12551146

申请日：2009-08-31

申请人： Li Gao ,  Alan Hendrickson

发明人： Li Gao ,  Alan Hendrickson

IPC分类号： H03L7/00 ,  H04N5/44 ,  H04N5/50 ,  H03D3/24 ,  H03D3/18 ,  H04B1/18

CPC分类号： H04N5/50 ,  H03L7/0805 ,  H03L7/1075 ,  H03L2207/50 ,  H04N21/4382 ,  H04N21/4383

摘要： In various implementations, a re-configurable phase lock loop may have multiple signal paths, including a feedforward path to operate in a carrier frequency acquisition mode to obtain a carrier frequency estimate and a feedback loop path to operate in a carrier frequency tracking mode to translate an incoming signal to a baseband signal. The multiple signal paths may share most of the hardware to reduce implementation cost.

摘要翻译： 在各种实施方案中，可重配置的锁相环可以具有多个信号路径，包括以载波频率获取模式操作以获得载波频率估计的前馈路径和以载波频率跟踪模式操作的反馈环路径 到基带信号的输入信号。 多个信号路径可以共享大多数硬件以降低实施成本。

公开(公告)号：US20110050998A1

公开(公告)日：2011-03-03

申请号：US12551146

申请日：2009-08-31

申请人： Li Gao ,  Alan Hendrickson

发明人： Li Gao ,  Alan Hendrickson

IPC分类号： H03L7/06 ,  H04N5/50

CPC分类号： H04N5/50 ,  H03L7/0805 ,  H03L7/1075 ,  H03L2207/50 ,  H04N21/4382 ,  H04N21/4383

摘要： In various implementations, a re-configurable phase lock loop may have multiple signal paths, including a feedforward path to operate in a carrier frequency acquisition mode to obtain a carrier frequency estimate and a feedback loop path to operate in a carrier frequency tracking mode to translate an incoming signal to a baseband signal. The multiple signal paths may share most of the hardware to reduce implementation cost.

摘要翻译： 在各种实施方案中，可重配置的锁相环可以具有多个信号路径，包括以载波频率获取模式操作以获得载波频率估计的前馈路径和以载波频率跟踪模式操作的反馈环路径 到基带信号的输入信号。 多个信号路径可以共享大多数硬件以降低实施成本。

公开(公告)号：US5974584A

公开(公告)日：1999-10-26

申请号：US974966

申请日：1997-11-20

申请人： Alan Hendrickson ,  Paul Schnizlein

发明人： Alan Hendrickson ,  Paul Schnizlein

IPC分类号： G06F11/00 ,  H03L7/093 ,  H03L7/099 ,  H03L7/107 ,  H03L7/14 ,  H03M13/00 ,  H04B1/707 ,  H04L1/24 ,  H04L7/033 ,  H04L27/00 ,  H04L27/22 ,  H04L27/227

CPC分类号： H04L27/2275 ,  H03L7/0991 ,  H03L7/107 ,  H03L7/146 ,  H04B1/707 ,  H04L1/24 ,  H04L27/22 ,  H04L27/2273 ,  H04L27/2277 ,  H03L7/093 ,  H04L2027/0028 ,  H04L2027/0046 ,  H04L2027/0067 ,  H04L2027/0069 ,  H04L7/0334

摘要： In a digital communication system for voice signals, a system and method for improving the quality of a received signal. The invention comprises a system for arranging the data and parity bits in a data frame and a corresponding method for analyzing and using the received frames. In the present invention, the data are conveyed in short independent segments, such as one or a few ADPCM nibbles. The length of each segment is chosen to be short enough that the loss of one segment of data from the received signal does not significantly degrade the quality of the output analog signal. The transmitter generates a parity bit for each of these segments and composes transmit frames by alternating data segments with their corresponding parity bits. The receiver then receives each data segment along with its corresponding parity bit. This arrangement allows the receiver to identify specific received segments that contain errors, and minimizes the receiver's delay between receiving the segment and determining if contains an error. The invention also comprises a system and method for detecting such an erroneous segment and blanking it. If a received frame contains more than a threshold number of erroneous segments, then the remaining segments of the frame can be muted. Subsequent frames can then also be muted until one of the subsequent frames contains fewer than a second threshold number of errors.

摘要翻译： 在用于语音信号的数字通信系统中，提供接收信号质量的系统和方法。 本发明包括一种用于在数据帧中布置数据和奇偶校验位的系统以及用于分析和使用所接收帧的相应方法。 在本发明中，数据在短的独立段中传送，例如一个或几个ADPCM半字节。 每个段的长度被选择为足够短，使得来自接收信号的一段数据的丢失不会显着降低输出模拟信号的质量。 发射机为这些段中的每一个生成一个奇偶校验位，并通过交替的数据段与它们对应的奇偶校验位组成发送帧。 然后接收器接收每个数据段及其对应的奇偶校验位。 这种布置允许接收机识别包含错误的特定接收段，并且最小化接收机在接收段之间的延迟并确定是否包含错误。 本发明还包括用于检测这样的错误段并将其消隐的系统和方法。 如果接收到的帧包含多于阈值数量的错误段，则帧的剩余段可以被静音。 随后的帧也可以被静音，直到后续帧之一包含少于第二阈值数量的错误。

公开(公告)号：US5266950A

公开(公告)日：1993-11-30

申请号：US942359

申请日：1992-09-09

申请人： Dale Gulick ,  Alan Hendrickson

发明人： Dale Gulick ,  Alan Hendrickson

IPC分类号： G06F3/023 ,  H04M1/26 ,  H03M11/00

CPC分类号： H04M1/26 ,  G06F3/0238

摘要： A keypad monitor implemented in an integrated circuit monitors the closure of a plurality of keypad switches coupled to input terminals of the integrated circuit. The keypad monitor is operative in a first mode for monitoring a first number of the input terminals and a second mode for monitoring a lesser number of input terminals. When in the second mode, the unmonitored input terminals are converted for a use not related to keypad monitoring.

摘要翻译： 在集成电路中实现的键盘监视器监视耦合到集成电路的输入端的多个键盘开关的闭合。 键盘监视器在第一模式下操作，用于监视第一数量的输入端子和用于监视较少数量的输入端子的第二模式。 当处于第二模式时，不受监控的输入端子被转换为与键盘监视无关的使用。

公开(公告)号：US20060179047A1

公开(公告)日：2006-08-10

申请号：US11334862

申请日：2006-01-19

申请人： David Bresemann ,  Alan Hendrickson ,  Robert Wagner

发明人： David Bresemann ,  Alan Hendrickson ,  Robert Wagner

IPC分类号： G06F17/30

CPC分类号： H01L23/544 ,  G05B2219/23336 ,  G06F9/4411 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2924/0002 ,  H01L2924/00

摘要： Programmable on-chip identification circuitry and associated method are disclosed that provide integrated circuits with the ability to select and report from multiple different vendor and system identification configurations. The integrated circuit device includes programmable circuitry that utilizes vendor identification, system identification, configuration or other device information provided or selected at least in part based upon selection information from a source external to the integrated circuit. The selection information may be provided through one or more externally generated digital and/or analog control signals that are then processed within the integrated circuit device to select, access and utilize desired identification information stored in an on-chip database. For example, one or more analog control signals can be generated using resistor circuits for which specific selectable resistor configurations map to particular information stored in a look-up table or other database structure within the integrated circuit. The analog control signals are converted to digital values within the integrated circuit, and these digital values are used to select device information from the on-chip database. Furthermore, the selected device information can be stored in on-chip device information registers. And the digital values themselves can be stored and used as identification, configuration or other device information.