公开(公告)号：US06948036B2

公开(公告)日：2005-09-20

申请号：US10177274

申请日：2002-06-21

申请人： Thomas W. Grieff ,  James R. Reif ,  Albert Chang

发明人： Thomas W. Grieff ,  James R. Reif ,  Albert Chang

IPC分类号： G06F3/06 ,  G06F11/00 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F3/0659 ,  G06F3/0607 ,  G06F3/0674

摘要： A multi-port adapter and method of operation suitable for use with serial ATA devices is disclosed. An adapter includes a switch that receives input from multiple host devices and an arbiter module for assigning a priority scheme to received commands. An outstanding request table is implemented as a memory module for storing identifying information associated with commands received from multiple host devices, and a free pointers queue is maintained to track slots available in the outstanding request table. A command tracker state machine decodes incoming requests from hosts, monitors the execution by these commands by the ATA device, and updates the memory module to reflect completion of commands. Also disclosed is a storage system including an adapter of the present invention and ATA storage devices.

摘要翻译： 公开了适用于串行ATA设备的多端口适配器和操作方法。 适配器包括从多个主机设备接收输入的交换机和用于向接收到的命令分配优先级方案的仲裁器模块。 一个未完成的请求表被实现为用于存储与从多个主机设备接收的命令相关联的识别信息的存储器模块，并且保持空闲指针队列以跟踪未完成请求表中可用的时隙。 命令跟踪器状态机解码来自主机的传入请求，通过ATA设备监视这些命令的执行，并更新内存模块以反映命令的完成。 还公开了一种包括本发明的适配器和ATA存储设备的存储系统。

公开(公告)号：US06961813B2

公开(公告)日：2005-11-01

申请号：US10373969

申请日：2003-02-25

申请人： Thomas Grieff ,  James R. Reif ,  Albert Chang

发明人： Thomas Grieff ,  James R. Reif ,  Albert Chang

IPC分类号： G06F3/06 ,  G06F11/00 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F3/0607 ,  G06F3/0659 ,  G06F3/0674

摘要： A multi-port adapter and method of operation suitable for use with serial ATA devices is disclosed. An adapter includes a switch that receives input from multiple host devices and an arbiter module for assigning a priority scheme to received commands. An outstanding request table is implemented as a memory module for storing identifying information associated with commands received from multiple host devices, and a free pointers queue is maintained to track slots available in the outstanding request table. A command tracker state machine decodes incoming requests from hosts, monitors the execution by these commands by the ATA device, and updates the memory module to reflect completion of commands. Also disclosed is a storage system including an adapter of the present invention and ATA storage devices.

公开(公告)号：US5237660A

公开(公告)日：1993-08-17

申请号：US289859

申请日：1988-12-27

申请人： Bret S. Weber ,  James R. Reif ,  Timothy E. Hoglund

发明人： Bret S. Weber ,  James R. Reif ,  Timothy E. Hoglund

IPC分类号： G06F5/10 ,  G06F5/14 ,  G06F13/42

CPC分类号： G06F5/14 ,  G06F13/423

摘要： A circuit for use with a SCSI interface for controlling synchronous data transfers into an attached FIFO memory. The circuit uses a comparator to keep track of the number of FIFO locations available by starting with a threshold value, which represents the locations available initially, and comparing the net number of FIFO locations filled to the threshold value. The net number of FIFO locations filled is kept by a counter which counts the difference between the words transferred into the FIFO and the words transferred out of the FIFO. The threshold value is an adjusted offset value if the SCSI interface is operating in INITIATOR mode, and the FIFO size if the SCSI interface is operating in TARGET mode. When the comparator determines that the FIFO is filled, it pauses the current synchronous message by withholding an ACK in the INITIATOR mode or a REQ in the TARGET mode.

摘要翻译： 用于与SCSI接口一起使用的电路，用于将同步数据传输到连接的FIFO存储器中。 电路使用比较器来跟踪可用的FIFO位置的数量，从阈值开始，阈值表示最初可用的位置，并且将填充的FIFO位置的净数与阈值进行比较。 填充的FIFO位置的净数由计数器计数，该计数器计数传输到FIFO中的字与从FIFO传送的字之间的差。 如果SCSI接口工作在INITIATOR模式，则该阈值是调整后的偏移值，如果SCSI接口工作在TARGET模式，则该值为FIFO大小。 当比较器确定FIFO被填充时，它通过在INITIATOR模式中保留ACK或者在目标模式中的REQ来暂停当前的同步消息。

公开(公告)号：US07028106B2

公开(公告)日：2006-04-11

申请号：US10728480

申请日：2003-12-05

申请人： Joseph E. Foster ,  Robert C. Elliott ,  Hubert E. Brinkmann, Jr. ,  James R. Reif

发明人： Joseph E. Foster ,  Robert C. Elliott ,  Hubert E. Brinkmann, Jr. ,  James R. Reif

IPC分类号： G06F13/00

CPC分类号： G06F13/404 ,  G06F13/4045

摘要： A system includes a peripheral device and an expander having interfaces to couple to one or more peripheral devices and an expander. The expander has a storage to store entries containing routing information used to route a request received by the expander to one of the interfaces, wherein each interface is allocated to a respective set of routing information entries. Mapping logic remaps unused routing information of one of the interfaces to one or more other interfaces to expand capacity of the one or more other interfaces.

摘要翻译： 一种系统包括具有耦合到一个或多个外围设备和扩展器的接口的外围设备和扩展器。 扩展器具有存储，用于存储包含用于将扩展器接收的请求路由到其中一个接口的路由信息​​的条目，其中每个接口被分配给相应的一组路由信息条目。 映射逻辑将其中一个接口的未使用路由信息重新映射到一个或多个其他接口，以扩展一个或多个其他接口的容量。

公开(公告)号：US5740454A

公开(公告)日：1998-04-14

申请号：US576193

申请日：1995-12-20

申请人： Philip C. Kelly ,  Todd J. DeSchepper ,  James R. Reif

发明人： Philip C. Kelly ,  Todd J. DeSchepper ,  James R. Reif

IPC分类号： G06F1/32

CPC分类号： G06F1/3228

摘要： A power management circuit for managing low power modes in a computer system, which implements four power modes, from highest power consumption to lowest power consumption: RUN mode, SLEEP mode, IDLE mode, and STAND BY mode. The computer system includes a PCI bus and an ISA bus, with a CPU-PCI bridge to connect the host bus and the PCI bus and a PCI-ISA bridge to connect the PCI bus and the ISA bus. The power management circuit transitions from SLEEP mode to IDLE mode by first determining if the CPU-PCI bridge is parked on the PCI bus and if it is in SLEEP mode. The power management circuit then waits for one refresh period and for all internal queues to empty before checking again to determine if the CPU-PCI bridge is still parked on the PCI bus and if it is still in SLEEP mode. If true, the CPU-PCI bridge transitions to IDLE mode. The power management circuit also performs low power refresh cycles when it is in IDLE or STANDBY mode. In those modes, the memory controller in the CPU-PCI bridge is disabled to conserve power. The power management circuit performs the refresh cycles based off an external asynchronous clock. Further, the power management circuit drives certain PCI bus signals to a certain state to avoid leakage current due to the existence of a mixture of 3.3-bolt and 5-volt components connected to the PCI bus.

摘要翻译： 一种用于管理计算机系统中的低功率模式的电源管理电路，其实现从最高功耗到最低功耗的四种功率模式：RUN模式，SLEEP模式，空闲模式和STAND BY模式。 计算机系统包括PCI总线和ISA总线，具有连接主机总线和PCI总线的CPU-PCI桥接器和用于连接PCI总线和ISA总线的PCI-ISA网桥。 电源管理电路首先确定CPU-PCI桥是否停放在PCI总线上，如果它处于休眠模式，则从休眠模式转换到空闲模式。 然后，电源管理电路等待一个刷新周期，并且所有内部队列都清空，然后再次检查以确定CPU-PCI桥是否仍然停留在PCI总线上，以及是否仍处于休眠模式。 如果为真，则CPU-PCI桥转换到空闲模式。 电源管理电路在空闲或待机模式下也执行低功耗刷新周期。 在这些模式下，CPU-PCI桥接器中的存储器控​​制器被禁用以节省电力。 电源管理电路基于外部异步时钟执行刷新周期。 此外，电源管理电路将某些PCI总线信号驱动到某一状态，以避免由于连接到PCI总线的3.3螺栓和5伏组件的混合存在而导致的漏电流。

公开(公告)号：US06357013B1

公开(公告)日：2002-03-12

申请号：US09042914

申请日：1998-03-17

申请人： Philip C. Kelly ,  Todd J. DeSchepper ,  James R. Reif

发明人： Philip C. Kelly ,  Todd J. DeSchepper ,  James R. Reif

IPC分类号： G06F132

CPC分类号： G06F1/3228

摘要： A power management circuit for managing low power modes in a computer system, which implements four power modes, from highest power consumption to lowest power consumption: RUN mode, SLEEP mode, IDLE mode, and STANDBY mode. The computer system includes a PCI bus and an ISA bus, with a CPU-PCI bridge to connect the host bus and the PCI bus and a PCI-ISA bridge to connect the PCI bus and the ISA bus. The power management circuit transitions from SLEEP mode to IDLE mode by first determining if the CPU-PCI bridge is parked on the PCI bus and if it is in SLEEP mode. The power management circuit then waits for one refresh period and for all internal queues to empty before checking again to determine if the CPU-PCI bridge is still parked on the PCI bus and if it is still in SLEEP mode. If true, the CPU-PCI bridge transitions to IDLE mode. The power management circuit also performs low power refresh cycles when it is in IDLE or STANDBY mode. In those modes, the memory controller in the CPU-PCI bridge is disabled to conserve power. The power management circuit performs the refresh cycles based off an external asynchronous clock. Further, the power management circuit drives certain PCI bus signals to a certain state to avoid leakage current due to the existence of a mixture of 3.3-bolt and 5-volt components connected to the PCI bus.

摘要翻译： 一种用于管理计算机系统中的低功率模式的电源管理电路，其实现从最高功耗到最低功耗的四种功率模式：RUN模式，SLEEP模式，空闲模式和待机模式。 计算机系统包括PCI总线和ISA总线，具有连接主机总线和PCI总线的CPU-PCI桥接器和用于连接PCI总线和ISA总线的PCI-ISA网桥。 电源管理电路首先确定CPU-PCI桥是否停放在PCI总线上，如果它处于休眠模式，则从休眠模式转换到空闲模式。 然后，电源管理电路等待一个刷新周期，并且所有内部队列都清空，然后再次检查以确定CPU-PCI桥是否仍然停留在PCI总线上，以及是否仍处于休眠模式。 如果为真，则CPU-PCI桥转换到空闲模式。 电源管理电路在空闲或待机模式下也执行低功耗刷新周期。 在这些模式下，CPU-PCI桥接器中的存储器控​​制器被禁用以节省电力。 电源管理电路基于外部异步时钟执行刷新周期。 此外，电源管理电路将某些PCI总线信号驱动到某一状态，以避免由于连接到PCI总线的3.3螺栓和5伏组件的混合存在而导致的漏电流。

公开(公告)号：US06230227B1

公开(公告)日：2001-05-08

申请号：US09209939

申请日：1998-12-11

申请人： Walter G. Fry ,  Todd J. Deschepper ,  James R. Reif

发明人： Walter G. Fry ,  Todd J. Deschepper ,  James R. Reif

IPC分类号： G06F1300

CPC分类号： G06F13/404

摘要： A computer system for supporting a subtractive agent on a secondary PCI bus is provided. A bridge resides between a primary PCI bus and a secondary PCI bus. Where both a master device and a target device reside on the secondary PCI bus, the bridge employs one of two protocols to permit successful completion of the transaction. The protocol used depends upon the type of transaction sought by the master device. Once the subtractive agent is identified by address, the bridge keeps track of its location. Thus, further operations targeting the subtractive agent run without requiring either protocol to be used. Further, the need for a specialized signaling protocol to access the subtractive agent is avoided.

摘要翻译： 提供了用于在辅助PCI总线上支持减法器的计算机系统。 桥接器位于主PCI总线和辅助PCI总线之间。 在主设备和目标设备驻留在辅助PCI总线上的情况下，桥接器使用两种协议之一来允许成功完成事务。 使用的协议取决于主设备所寻求的事务类型。 一旦通过地址识别减法器，桥就会跟踪其位置。 因此，靶向减法器的进一步操作不需要使用任何协议。 此外，避免需要专门的信令协议来访问减法器。

公开(公告)号：US5867728A

公开(公告)日：1999-02-02

申请号：US768308

申请日：1996-12-17

申请人： Maria L. Melo ,  James R. Reif

发明人： Maria L. Melo ,  James R. Reif

IPC分类号： G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4027

摘要： To assure that memory and/or I/O cycles will run correctly after a PCI device configuration cycle that changes memory and/or I/O mapping, in a multi-processor P6 computer system that pipelines instructions. The memory and I/O cycles are suspended on the processor bus until the configuration cycle has been completed. A signal is generated within the address decode logic to prevent address decoding from taking place if a PCI device is being configured. During the configuration transactions, other pipelined transaction cycles are snoop stalled until the PCI configuration write has been completed.

摘要翻译： 为了确保内存和/或I / O周期在更改内存和/或I / O映射的PCI设备配置周期后能够在管理指令的多处理器P6计算机系统中正常运行。 存储器和I / O周期暂停在处理器总线上，直到配置周期完成。 在地址解码逻辑中产生信号，以防止在配置PCI设备时发生地址解码。 在配置事务期间，其他流水线事务周期被窥探停止，直到PCI配置写入完成。

公开(公告)号：US06243817B1

公开(公告)日：2001-06-05

申请号：US08995703

申请日：1997-12-22

申请人： Maria L. Melo ,  James R. Reif ,  David J. Maguire

发明人： Maria L. Melo ,  James R. Reif ,  David J. Maguire

IPC分类号： G06F126

CPC分类号： G06F1/3253 ,  G06F1/3203 ,  Y02D10/151

摘要： A computer is provided having a bus interface unit coupled between a CPU bus and a mezzanine bus, or PCI bus. The bus interface unit includes a plurality of input buffers which can be selectively connected and disconnected in a dynamic fashion according to active and inactive signals forwarded thereto. Signals forwarded to the bus interface unit from the CPU are classified according to the transaction phase of CPU bus activity. If signals associated with one particular transaction phase are active, then input buffers attributed to signals of other transaction phases can be deactivated. It is preferred that input buffers associated with signals of a request and arbitration phase be maintained active and coupled to power regardless of the present transaction phase unless the computer enters a powered down mode, such as sleep, idle or standby.

摘要翻译： 提供了一种具有耦合在CPU总线和夹层总线或PCI总线之间的总线接口单元的计算机。 总线接口单元包括多个输入缓冲器，其可以根据转发给其的有源和非活动信号以动态方式选择性地连接和断开。 根据CPU总线活动的事务阶段对从CPU传送到总线接口单元的信号进行分类。 如果与一个特定事务阶段相关联的信号是有效的，则归因于其他事务阶段的信号的输入缓冲器可以被去激活。 优选的是，与请求和仲裁阶段的信号相关联的输入缓冲器保持有效并且与当前事务阶段无关地耦合到功率，除非计算机进入诸如睡眠，空闲或待机的断电模式。

公开(公告)号：US5796992A

公开(公告)日：1998-08-18

申请号：US575370

申请日：1995-12-20

申请人： James R. Reif ,  Michael J. Collins ,  Todd J. DeSchepper

发明人： James R. Reif ,  Michael J. Collins ,  Todd J. DeSchepper

IPC分类号： G06F1/32 ,  G06F1/04

CPC分类号： G06F1/32

摘要： A power management circuit for managing low power modes in a computer system, which implements four power modes, from highest power consumption to lowest power consumption: RUN mode, SLEEP mode, IDLE mode, and STANDBY mode. The computer system includes a PCI bus and an ISA bus, with a CPU-PCI bridge to connect the host bus and the PCI bus and a PCI-ISA bridge to connect the PCI bus and the ISA bus. The power management circuit transitions from SLEEP mode to IDLE mode by first determining if the CPU-PCI bridge is parked on the PCI bus and if it is in SLEEP mode. The power management circuit then waits for one refresh period and for all internal queues to empty before checking again to determine if the CPU-PCI bridge is still parked on the PCI bus and if it is still in SLEEP mode. If true, the CPU-PCI bridge transitions to IDLE mode. The power management circuit also performs low power refresh cycles when it is in IDLE or STANDBY mode. In those modes, the memory controller in the CPU-PCI bridge is disabled to conserve power. The power management circuit performs the refresh cycles based off an external asynchronous clock. Further, the power management circuit drives certain PCI bus signals to a certain state to avoid leakage current due to the existence of a mixture of 3.3-volt and 5-volt components connected to the PCI bus.

摘要翻译： 一种用于管理计算机系统中的低功率模式的电源管理电路，其实现从最高功耗到最低功耗的四种功率模式：RUN模式，SLEEP模式，空闲模式和待机模式。 计算机系统包括PCI总线和ISA总线，具有连接主机总线和PCI总线的CPU-PCI桥接器和用于连接PCI总线和ISA总线的PCI-ISA网桥。 电源管理电路首先确定CPU-PCI桥是否停放在PCI总线上，如果它处于休眠模式，则从休眠模式转换到空闲模式。 然后，电源管理电路等待一个刷新周期，并且所有内部队列都清空，然后再次检查以确定CPU-PCI桥是否仍然停留在PCI总线上，以及是否仍处于休眠模式。 如果为真，则CPU-PCI桥转换到空闲模式。 电源管理电路在空闲或待机模式下也执行低功耗刷新周期。 在这些模式下，CPU-PCI桥接器中的存储器控​​制器被禁用以节省电力。 电源管理电路基于外部异步时钟执行刷新周期。 此外，电源管理电路将某些PCI总线信号驱动到某一状态，以避免由于存在连接到PCI总线的3.3伏和5伏组件的混合而引起的漏电流。