Method and system for component sync detection and alignment
    1.
    发明授权
    Method and system for component sync detection and alignment 失效
    用于组件同步检测和对齐的方法和系统

    公开(公告)号:US07359005B2

    公开(公告)日:2008-04-15

    申请号:US10975744

    申请日:2004-10-28

    IPC分类号: H04N9/475

    CPC分类号: H04N5/10 H04N5/08 H04N9/641

    摘要: In a method and system for component sync detection and alignment, the Y/G channel is used as a master channel from which the vertical and the horizontal syncs are detected by a master sync generator. The master sync generator determines a fast and slow slice level for generating a rough and a fractional detection of the vertical sync and the horizontal sync and also generates a master sync timing window signal. A slave sync generator aligns the Pb/B and Pr/R channels to the Y/G channel by making use of the vertical, horizontal, and timing window sync signals produced by the master sync generator and by generating a slave slice level to detect the vertical and horizontal syncs in the slave channels. Positional differences in the alignment between the master channel and the slave channels are determined and stored for use in subsequent frame alignment.

    摘要翻译: 在用于组件同步检测和对准的方法和系统中,Y / G通道用作主通道,垂直和水平同步由主同步发生器从其中检测。 主同步发生器确定用于产生垂直同步和水平同步的粗略和分数检测的快速和慢速切片电平,并且还产生主同步定时窗口信号。 从同步发生器通过利用由主同步发生器产生的垂直,水平和定时窗口同步信号,并通过产生从属片级来检测第一和第二信号,从而将Pb / B和Pr / R信道对准Y / G信道 从属通道中的垂直和水平同步。 主通道和从通道之间对准的位置差异被确定和存储以用于随后的帧对准。

    Method and system for component sync detection and alignment
    2.
    发明申请
    Method and system for component sync detection and alignment 失效
    用于组件同步检测和对齐的方法和系统

    公开(公告)号:US20050190294A1

    公开(公告)日:2005-09-01

    申请号:US10975744

    申请日:2004-10-28

    IPC分类号: H04N5/08 H04N5/10 H04N9/64

    CPC分类号: H04N5/10 H04N5/08 H04N9/641

    摘要: In a method and system for component sync detection and alignment, the Y/G channel is used as a master channel from which the vertical and the horizontal syncs are detected by a master sync generator. The master sync generator determines a fast and slow slice level for generating a rough and a fractional detection of the vertical sync and the horizontal sync and also generates a master sync timing window signal. A slave sync generator aligns the Pb/B and Pr/R channels to the Y/G channel by making use of the vertical, horizontal, and timing window sync signals produced by the master sync generator and by generating a slave slice level to detect the vertical and horizontal syncs in the slave channels. Positional differences in the alignment between the master channel and the slave channels are determined and stored for use in subsequent frame alignment.

    摘要翻译: 在用于组件同步检测和对准的方法和系统中,Y / G通道用作主通道,垂直和水平同步由主同步发生器从其中检测。 主同步发生器确定用于产生垂直同步和水平同步的粗略和分数检测的快速和慢速切片电平,并且还产生主同步定时窗口信号。 从同步发生器通过利用由主同步发生器产生的垂直,水平和定时窗口同步信号,并通过生成从属片级来检测到该片段级别,从而将Pb / B和Pr / R信道对准Y / G信道 从属通道中的垂直和水平同步。 主通道和从通道之间对准的位置差异被确定和存储以用于随后的帧对准。

    Method and System for Automatic Phase Locking of Analog Inputs
    3.
    发明申请
    Method and System for Automatic Phase Locking of Analog Inputs 审中-公开
    模拟输入自动锁相的方法和系统

    公开(公告)号:US20080192143A1

    公开(公告)日:2008-08-14

    申请号:US11672755

    申请日:2007-02-08

    IPC分类号: H03L7/00

    CPC分类号: H03L7/06

    摘要: Methods and systems for automatic phase locking of analog inputs are disclosed. Aspects of one method may include calibrating one of a plurality of video signals. A next phase for a sampling clock may be determined via the calibration, and a phase of the sampling clock may be adjusted to the determined next phase. The samples generated using the sampling clocks may be displayed on a video display, while the samples generated using the calibration clock may not be displayed on a video display.

    摘要翻译: 公开了用于自动锁相模拟输入的方法和系统。 一种方法的方面可以包括校准多个视频信号之一。 可以经由校准来确定采样时钟的下一个相位,并且采样时钟的相位可以被调整到确定的下一个相位。 使用采样时钟生成的样本可以显示在视频显示器上,而使用校准时钟生成的样本可能不会显示在视频显示器上。

    Closed loop sub-carrier synchronization system
    5.
    发明授权
    Closed loop sub-carrier synchronization system 失效
    闭环子载波同步系统

    公开(公告)号:US07529330B2

    公开(公告)日:2009-05-05

    申请号:US12118124

    申请日:2008-05-09

    IPC分类号: H04L7/00

    CPC分类号: H04N9/78 H04N9/44

    摘要: A system and method for synchronizing sub-carriers in a signal processing system. Various aspects of the present invention may comprise method steps and structure that receive a sampled signal. Various aspects may produce a synchronization signal based on the sampled signal. Various aspects may generate and store a cropped version of the received sampled signal. Various aspects may read a cropped sampled signal from memory that corresponds to the received sampled signal. Various aspects may generate a restored sampled signal by adding samples to the cropped sampled signal read from memory. Various aspects may, based on the synchronization signal, output the restored sampled signal coarsely synchronized to the received sampled signal. Various aspects may determine a phase difference between the output restored sampled signal and the output received sub-carrier. Various aspects may adjust the phase of the restored sampled signal in response to the determined phase difference.

    摘要翻译: 一种用于在信号处理系统中同步子载波的系统和方法。 本发明的各个方面可以包括接收采样信号的方法步骤和结构。 各个方面可以基于采样信号产生同步信号。 各方面可以生成并存储所接收的采样信号的裁剪版本。 各个方面可以从对应于接收到的采样信号的存储器读取经裁剪的采样信号。 各个方面可以通过将样本添加到从存储器读取的经裁剪的采样信号来产生恢复的采样信号。 各个方面可以基于同步信号,将恢复的采样信号粗略地与接收的采样信号同步。 各个方面可以确定输出恢复的采样信号和输出接收的子载波之间的相位差。 响应于确定的相位差,各个方面可以调整恢复的采样信号的相位。

    Closed loop sub-carrier synchronization system
    6.
    发明授权
    Closed loop sub-carrier synchronization system 有权
    闭环子载波同步系统

    公开(公告)号:US07372929B2

    公开(公告)日:2008-05-13

    申请号:US10794601

    申请日:2004-03-05

    IPC分类号: H04L7/00

    CPC分类号: H04N9/78 H04N9/44

    摘要: A system and method for synchronizing sub-carriers in a signal processing system. Various aspects of the present invention may comprise method steps and structure that receive a sampled signal. Various aspects may produce a synchronization signal based on the sampled signal. Various aspects may generate and store a cropped version of the received sampled signal. Various aspects may read a cropped sampled signal from memory that corresponds to the received sampled signal. Various aspects may generate a restored sampled signal by adding samples to the cropped sampled signal read from memory. Various aspects may, based on the synchronization signal, output the restored sampled signal coarsely synchronized to the received sampled signal. Various aspects may determine a phase difference between the output restored sampled signal and the output received sub-carrier. Various aspects may adjust the phase of the restored sampled signal in response to the determined phase difference.

    摘要翻译: 一种用于在信号处理系统中同步子载波的系统和方法。 本发明的各个方面可以包括接收采样信号的方法步骤和结构。 各个方面可以基于采样信号产生同步信号。 各方面可以生成并存储所接收的采样信号的裁剪版本。 各个方面可以从对应于接收到的采样信号的存储器读取经裁剪的采样信号。 各个方面可以通过将样本添加到从存储器读取的经裁剪的采样信号来产生恢复的采样信号。 各个方面可以基于同步信号,将恢复的采样信号粗略地与接收的采样信号同步。 各个方面可以确定输出恢复的采样信号和输出接收的子载波之间的相位差。 响应于确定的相位差,各个方面可以调整恢复的采样信号的相位。

    Method and system for providing a hardware sort for a large number of items
    7.
    发明授权
    Method and system for providing a hardware sort for a large number of items 有权
    为大量物品提供硬件排序的方法和系统

    公开(公告)号:US07363304B2

    公开(公告)日:2008-04-22

    申请号:US10882035

    申请日:2004-06-29

    IPC分类号: G06F17/30 G06F15/00 G06F17/50

    CPC分类号: G06F7/36 Y10S707/99937

    摘要: A method and system for sorting a number of items in a computer system. The sort is based on a plurality of values of a key. Each item has a value of the plurality of values. The method and system include providing plurality of stages, providing at least one switch coupled between the plurality of stages, and providing a final switch coupled with a last stage. Each of the plurality of stages has a pair of first-in-first-out buffers (FIFOs) that store twice as many of the items as the pair of FIFOs in a previous stage. Each switch is for merging and sorting a first portion of the number of items from the pair of FIFOs in the previous stage based on the key and for providing the first portion of the number plurality of items to a first FIFO of the pair of FIFOs of the stage in order. Each switch is also for merging and sorting a second portion of the number of items the pair of FIFOs in the previous stage based on the key and providing the second portion of the number plurality of items to a second FIFO of the pair of FIFOs of the stage in order. The last switch is for merging and sorting a third portion of the number of items to provide the number of items in order.

    摘要翻译: 一种用于对计算机系统中的多个物品进行排序的方法和系统。 该排序基于密钥的多个值。 每个项目具有多个值的值。 该方法和系统包括提供多个级,提供耦合在多个级之间的至少一个开关,以及提供与最后级相连的最终开关。 多个级中的每一个具有一对先前先出的缓冲器(FIFO),其存储与前一级中的FIFO对相同的数量的两倍。 每个交换机用于根据密钥对来自前一级的FIFO对中的项目数量的第一部分进行合并和排序,并且用于将数量多个项目的第一部分提供给该对FIFO的第一FIFO 阶段顺序。 每个交换机还用于根据密钥对前一级中的一对FIFO的项目数量的第二部分进行合并和排序,并将数量多个项目的第二部分提供给该对的FIFO对的第二FIFO 阶段顺序。 最后一个开关是为了mer

    Method and system for data compression for storage of 3D comb filter data
    8.
    发明申请
    Method and system for data compression for storage of 3D comb filter data 有权
    用于存储3D梳状滤波器数据的数据压缩方法和系统

    公开(公告)号:US20050174492A1

    公开(公告)日:2005-08-11

    申请号:US10869395

    申请日:2004-06-16

    IPC分类号: H04N9/64 H04N9/78

    CPC分类号: H04N9/78

    摘要: Methods and systems for data compression for storage of 3D comb filter data are disclosed. An incoming video signal may be band-limited during combing, where the incoming video signal may comprise a plurality of active and inactive video samples disposed within a plurality of video lines. The active video samples disposed within at least a portion of the plurality of video lines may be stored. The incoming video signal may be band-limited to 6.75 MHz, for example. Video samples utilized for eliminating edge effects may be stored. The number of video samples utilized for eliminating edge effects may be associated with an upsampling filter tap count. The active video samples may be combed. At least a portion of the plurality of video lines may be stored. The portion of the plurality of video lines may comprise active video lines.

    摘要翻译: 公开了用于存储3D梳状滤波器数据的数据压缩的方法和系统。 输入视频信号可以在梳理期间被带限制,其中输入视频信号可以包括设置在多个视频行内的多个有效和非活动视频样本。 可以存储设置在多个视频行的至少一部分内的活动视频样本。 输入的视频信号例如可以被限制到6.75MHz。 可以存储用于消除边缘效应的视频样本。 用于消除边缘效应的视频样本的数量可能与上采样滤波器抽头数相关。 活动的视频样本可以被梳理。 多个视频行的至少一部分可以被存储。 多个视频行的部分可以包括有效的视频行。

    Systems and methods for generation of time-dependent control signals for video signals
    9.
    发明申请
    Systems and methods for generation of time-dependent control signals for video signals 有权
    用于产生视频信号的时间依赖控制信号的系统和方法

    公开(公告)号:US20050036764A1

    公开(公告)日:2005-02-17

    申请号:US10640627

    申请日:2003-08-14

    摘要: Systems and methods for generation of time-dependent control signals for video signals are provided. A system is provided that includes a set of microsequencers, a programmable combinational logic (PCL) module, shared memory, an arbiter for sharing of memory by the microsequencers, stacks containing registers for microsequencer control, and a control interface. The system can efficiently provide control signals for video signals, implement the MACROVISION copy protection process, and provide other value added features. The method includes accessing programs from shared memory, such that a set of microsequencers can generate flags. These flags are then processed to generate one or more control signals used to support the outputting of video signals including those requiring MACROVISION copy protection.

    摘要翻译: 提供了用于产生用于视频信号的时间相关控制信号的系统和方法。 提供了一种系统,其包括一组微排序器,可编程组合逻辑(PCL)模块,共享存储器,用于由微排序器共享存储器的仲裁器,包含用于微定序器控制的寄存器的堆栈和控制接口。 该系统可以有效地为视频信号提供控制信号,实现MACROVISION复制保护过程,并提供其他增值功能。 该方法包括从共享存储器访问程序,使得一组微排序器可以产生标志。 然后处理这些标志以产生用于支持输出视频信号的一个或多个控制信号,包括需要MACROVISION复制保护的视频信号。

    Technique for generating on-screen display characters using software
implementation
    10.
    发明授权
    Technique for generating on-screen display characters using software implementation 失效
    使用软件实现生成屏幕显示字符的技术

    公开(公告)号:US6072462A

    公开(公告)日:2000-06-06

    申请号:US688426

    申请日:1996-07-30

    IPC分类号: H04N5/445 G09G5/22

    摘要: A method for generating a video character in an on-screen display system. The method uses a HALT signal provided to the microprocessor which allows the microprocessor to finish executing its current instruction, but prohibits the microprocessor from beginning a next instruction. After a sufficient amount of time has passed to ensure that the microprocessor has completed its current instruction, an OSD interrupt signal is sent to the microprocessor instructing the microprocessor to begin OSD operations. Alternatively, the method uses a bus multiplexer which duplicates character data and sends the expanded data to a bus in order to enlarge characters displayed on the screen.

    摘要翻译: 一种用于在屏幕显示系统中生成视频字符的方法。 该方法使用提供给微处理器的HALT信号,允许微处理器完成其当前指令的执行,但是禁止微处理器开始下一条指令。 在经过足够的时间以确保微处理器已经完成其当前指令之后,OSD中断信号被发送到微处理器,指示微处理器开始OSD操作。 或者,该方法使用复制字符数据的总线多路复用器,并将扩展数据发送到总线,以便放大显示在屏幕上的字符。