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11 条记录 (耗时 0.014 秒)

    Method and system for ensuring the assertion order of signals in a chip independent of physical layout
    4.
    发明授权
    Method and system for ensuring the assertion order of signals in a chip independent of physical layout 有权

    公开(公告)号：US07102397B2

    公开(公告)日：2006-09-05

    申请号：US10961015

    申请日：2004-10-08

    申请人： James D. Sweet

    发明人： James D. Sweet

    IPC分类号： H03L7/00

    CPC分类号： H03K19/1731 ,  G01R31/31701

    摘要： Certain embodiments for ensuring the assertion order of signals in a chip independent of physical layout may comprise receiving a first signal by a first logic block of a plurality of logic blocks integrated within a chip, where the first signal may initiate a reset of a first function within the first logic block. A second signal may be communicated from within the first logic block to a second function within a second logic block of the plurality of logic blocks, and the second signal may be adapted to initiate the second function. The first signal may be the same as a second signal. The reset of the first function may initialize the first function to a known state before the second function may generate an output that may be received by the first function. The first function may place the chip in a test mode when indicated by the generated output of the second function.

    System and method using an I/O multiplexer module
    6.
    发明授权
    System and method using an I/O multiplexer module 有权
    使用I / O复用器模块的系统和方法

    公开(公告)号：US07532648B2

    公开(公告)日：2009-05-12

    申请号：US10640649

    申请日：2003-08-14

    申请人： James D Sweet

    发明人： James D Sweet

    IPC分类号： H04J3/04

    CPC分类号： H04N21/426 ,  H04N5/4401 ,  H04N5/46 ,  H04N7/035 ,  H04N21/4263 ,  H04N2005/91364

    摘要： A system (e.g., a chip) includes first and second function blocks (e.g., function blocks) coupled to an input/output (I/O) device (e.g., a bi-directional pin or pad) via a multiplexing module. The multiplexing module can be used for both input and output of signals between the function blocks and the I/O device. Optionally, a re-clocking system is coupled to the function blocks, the I/O device, and the multiplexing module. The re-clocking system re-clocks one or more signals being input into the multiplexing module so that they are timed correctly for input or output from the system.

    摘要翻译： 系统（例如，芯片）包括经由复用模块耦合到输入/输出（I / O）设备（例如，双向引脚或焊盘）的第一和第二功能块（例如，功能块）。 复用模块可用于功能块和I / O设备之间的信号输入和输出。 可选地，重新计时系统耦合到功能块，I / O设备和多路复用模块。 重新计时系统将输入到复用模块中的一个或多个信号重新计时，使得它们被正确地定时输入或输出系统。

    Testing of integrated circuits from design documentation
    8.
    发明授权
    Testing of integrated circuits from design documentation 失效
    从设计文件测试集成电路

    公开(公告)号：US06978216B2

    公开(公告)日：2005-12-20

    申请号：US10703729

    申请日：2003-11-07

    申请人： James D. Sweet

    发明人： James D. Sweet

    IPC分类号： G01R31/3183 ,  G06F17/50 ,  G06F19/00

    CPC分类号： G01R31/318357 ,  G01R31/318342 ,  G06F17/5022

    摘要： One or more methods and systems of validating the operation of one or more register designs are presented. In one embodiment, the system utilizes a processor, an integrated circuit design simulator software, a storage media, a storage device, user interface, and a display. In one embodiment, the method includes executing a set of instructions operating on a register design parameter file to produce an output that is easily incorporated into the integrated circuit design simulator software. The output specifies one or more tests to be performed using the integrated circuit design simulator software. The one or more tests are subsequently performed to validate the register design. The method automates the incorporation of register design parameters into the integrated circuit design simulator software by way of executing a set of instructions that operates on the register design parameter file.

    摘要翻译： 提出一种或多种验证一个或多个寄存器设计的操作的方法和系统。 在一个实施例中，系统利用处理器，集成电路设计模拟器软件，存储介质，存储设备，用户界面和显示器。 在一个实施例中，该方法包括执行在寄存器设计参数文件上操作的一组指令以产生易于并入到集成电路设计仿真器软件中的输出。 输出指定使用集成电路设计模拟器软件执行的一个或多个测试。 随后执行一个或多个测试以验证寄存器设计。 该方法通过执行对寄存器设计参数文件进行操作的一组指令来自动将寄存器设计参数并入到集成电路设计仿真器软件中。

    System and method having strapping with override functions
    10.
    发明授权
    System and method having strapping with override functions 有权
    具有覆盖功能的系统和方法

    公开(公告)号：US07263627B2

    公开(公告)日：2007-08-28

    申请号：US10641103

    申请日：2003-08-15

    申请人： James D Sweet ,  Thu T Nguyen

    发明人： James D Sweet ,  Thu T Nguyen

    IPC分类号： G06F1/12 ,  G06F13/42 ,  H04L5/00 ,  H04L7/00

    CPC分类号： H04N21/426 ,  H04N5/4401 ,  H04N5/46 ,  H04N7/035 ,  H04N21/4263 ,  H04N2005/91364

    摘要： A system and method allow for overriding of a strapping option. A strapping signal places a device (e.g., a processor) in first state or mode (e.g., client or master). An override system places the device in a second state or mode. The second state or mode can be temporary. The changing of the state or mode of the device can be used to perform testing of the chip, during which a memory is written to and read from to verify operation of the chip. The second state or mode of the device may also be used to allow the device to perform alternative functions that are not available during its first state or mode.

    摘要翻译： 系统和方法允许覆盖捆绑选项。 捆扎信号将设备（例如，处理器）置于第一状态或模式（例如，客户端或主机）。 覆盖系统将设备置于第二状态或模式。 第二种状态或模式可以是临时的。 可以使用设备的状态或模式的改变来执行芯片的测试，在此期间，存储器被写入和读取以验证芯片的操作。 设备的第二状态或模式也可以用于允许设备执行在其第一状态或模式期间不可用的替代功能。