公开(公告)号：US06597748B1

公开(公告)日：2003-07-22

申请号：US09980302

申请日：2001-11-28

申请人： Alex Hietala ,  Nadim Khlat ,  Patrick Clement

发明人： Alex Hietala ,  Nadim Khlat ,  Patrick Clement

IPC分类号： H04L2716

CPC分类号： H04B1/30

摘要： Apparatus 20, 30, 50, 60 for receiving a carrier signal modulated by a wanted signal, the modulated carrier signal occupying one of a plurality of channels whose central frequencies are separated from one another by a fixed frequency referred to as the channel spacing, the apparatus including a local oscillator 28 for generating first and second signals at a frequency which is not an integral multiple of half the channel spacing whereby when the received carrier signal is mixed with the first and second signals, a complex, digital Very Low Intermediate Frequency (VLIF) signal is generated in which the wanted signal is centred about a VLIF which is slightly larger than half the channel spacing.

摘要翻译： 用于接收由有用信号调制的载波信号的装置20,30,50,60，调制载波信号占据多个信道中的一个，其中心频率被称为信道间隔的固定频率， 该设备包括本地振荡器28，用于以不是信道间隔的一半的整数倍的频率产生第一和第二信号，由此当接收的载波信号与第一和第二信号混合时，复数数字非常低的中频 VLIF）信号，其中有用信号以略大于信道间隔的一半的VLIF为中心。

公开(公告)号：US20060145900A1

公开(公告)日：2006-07-06

申请号：US10515561

申请日：2003-05-19

申请人： Patrick Clement ,  Nadim Khlat

发明人： Patrick Clement ,  Nadim Khlat

IPC分类号： H03M3/00

CPC分类号： H03M3/466 ,  H03M3/41

摘要： An arrangement (100) and method for sigma-delta analog-to-digital conversion by providing parallel translating sigma-delta analog-to-digital converters (21, 22) and summing their outputs to produce a digital output signal having a bandwidth greater than that of the first or second translating sigma-delta analog-to-digital converters (21, 22). The parallel translating sigma-delta analog-to-digital converters (21, 22) use switching sequences arranged to cancel third and fifth harmonics in the digital output signal. Orthogonality error in the switching sequences applied to the sigma-delta modulators is compensated by adjusting the phase of the signals applied to mixers (51, 52).

摘要翻译： 一种用于通过提供并行转换Σ-Δ模数转换器（21,22）并对其输出进行求和以产生具有大于或等于的带宽的数字输出信号的Σ-Δ模数转换的装置（100）和方法 第一或第二平移Σ-Δ模数转换器（21,22）的转换。 并行转换Σ-Δ模数转换器（21,22）使用布置成消除数字输出信号中的第三和第五谐波的开关序列。 通过调整施加到混合器（51,52）的信号的相位来补偿施加到Σ-Δ调制器的开关序列中的正交性误差。

公开(公告)号：US06856266B2

公开(公告)日：2005-02-15

申请号：US10490875

申请日：2002-09-09

申请人： Patrick Clement ,  Nadim Khlat ,  Daniel B Schwartz

发明人： Patrick Clement ,  Nadim Khlat ,  Daniel B Schwartz

IPC分类号： H03M3/02 ,  H03M3/00 ,  H03M1/00 ,  H03M7/00

CPC分类号： H03M3/496

摘要： A Multi-Rate Analog-to-Digital Converter (19) is coupled to a single crystal oscillator (17) as a reference clock and has at least two separate channels arranged to sample and convert input data at two differing clock rates. Each channel derives a clock signal from the reference clock. Associated with each of the channels is a Sigma-Delta converter (10a, 10b) comprising a modulator (12), a filter (14) and a resampler (18). The modulator (12) receives input data and provides a data signal to the filter (14), which itself provides a filtered data signal to the associated data resampler. The data resampler resamples the data and provides a digital output signal. As there is sampling in the digital domain the advantages associated with signal processing, speed and low noise injection are obtained. Similarly as the output of the modulator (12) is in digital form, it can be manipulated and processed readily and with the existing software.

摘要翻译： 多速率模数转换器（19）耦合到作为参考时钟的单晶振荡器（17），并且具有至少两个单独的通道，其布置成以两个不同的时钟速率对输入数据进行采样和转换。 每个通道从参考时钟导出时钟信号。 与每个通道相关联的是包括调制器（12），滤波器（14）和重采样器（18）的Σ-Δ转换器（10a，10b）。 调制器（12）接收输入数据并向滤波器（14）提供数据信号，滤波器本身将经过滤波的数据信号提供给相关联的数据重采样器。 数据重采样器重新采样数据并提供数字输出信号。 由于在数字领域中采用了与信号处理，速度和低噪声注入相关的优点。 类似地，当调制器（12）的输出是数字形式时，它可以容易地和现有的软件被操纵和处理。

公开(公告)号：US06678340B1

公开(公告)日：2004-01-13

申请号：US09535396

申请日：2000-03-24

申请人： Nadim Khlat ,  Patrick Clement

发明人： Nadim Khlat ,  Patrick Clement

IPC分类号： H04B110

CPC分类号： H03D3/007 ,  H03D7/166

摘要： Apparatus 20,30,40,50 for receiving and processing a wanted Radio Frequency signal comprises a radio frequency to intermediate frequency down-conversion stage 20 for receiving the wanted radio frequency signal and out-putting a complex intermediate frequency signal; an analogue to digital converter 30 for converting the complex intermediate frequency signal to a digital complex intermediate signal; an intermediate frequency to base-band down-conversion stage 40 for receiving the digital complex intermediate frequency signal and out-putting a digital complex base-band signal; and a complex notch filter 50 for receiving the digital complex base-band signal and out-putting a notch filtered digital complex base-band signal wherein the complex notch filter 50 substantially filters out a small portion of the base-band signal centred about a first, non-zero, frequency while substantially passing a corresponding portion of the base-band signal centred about a second frequency having the same magnitude but opposite sign to the first frequency.

摘要翻译： 用于接收和处理所需射频信号的设备20,30,40,50包括用于接收所需射频信号并输出​​复合中频信号的射频至中频下变频级20; 用于将复合中频信号转换为数字复合中间信号的模数转换器30; 中频到基带下变频级40，用于接收数字复合中频信号并输出​​数字复基带信号; 以及用于接收数字复基带信号并输出​​陷波滤波的数字复基带信号的复陷波滤波器50，其中复陷波滤波器50基本上过滤掉以第一和第二信号为中心的基带信号的一小部分 ，非零频率，同时基本上将以具有相同幅度但相反符号的第二频率为中心的基带信号的对应部分传送到第一频率。

公开(公告)号：US06356594B1

公开(公告)日：2002-03-12

申请号：US09431482

申请日：1999-11-02

申请人： Patrick Clement ,  Nadim Khlat

发明人： Patrick Clement ,  Nadim Khlat

IPC分类号： H04L2302

CPC分类号： H03C3/403 ,  H03D3/007 ,  H03D7/166 ,  H03M3/40 ,  H03M3/458 ,  H03M3/50

摘要： An analogue to digital or digital to analogue data converter 1 for converting between a first digital signal 101,102 at a first sampling rate fo and a first analogue signal 171,172, comprises a first conversion stage 11,12,21,22,31,32 for converting an input signal 101,102 into an intermediate digital signal 131,132 at a second sampling rate fsm which is greater than the first over-sampling rate fo; a processing stage 30,41,42,43,44,51,52 for performing digital signal processing on the intermediate digital signal to generate a processed intermediate digital signal 151,152; and a second conversion stage 61,62,71,72 for converting the processed intermediate digital signal into an output signal 171,172, wherein the input and output signals comprise the first analogue signal and the first digital signal or vice versa depending on whether the data converter is performing analogue to digital or digital to analogue conversion.

摘要翻译： 用于在第一采样率fo的第一数字信号101,102和第一模拟信号171,172之间转换的模拟数字或数模转换器1包括用于转换的第一转换级11,12,21,22,31,32 以大于第一过采样率fo的第二采样率fsm将输入信号101,102转换成中间数字信号131,132; 用于对中间数字信号执行数字信号处理以产生经处理的中间数字信号151,152的处理级30,41,42,43,44,51,52; 以及用于将经处理的中间数字信号转换成输出信号171,172的第二转换级61,62,71,72，其中输入和输出信号包括第一模拟信号和第一数字信号，反之亦然，取决于数据转换器 正在进行模数转换或数模转换。

公开(公告)号：US20050001748A1

公开(公告)日：2005-01-06

申请号：US10490875

申请日：2002-09-09

申请人： Patrick Clement ,  Nadim Khlat ,  Daniel Schwartz

发明人： Patrick Clement ,  Nadim Khlat ,  Daniel Schwartz

IPC分类号： H03M3/02 ,  H03M3/00

CPC分类号： H03M3/496

摘要： A Multi-Rate Analog-to-Digital Converter (19) is coupled to a single crystal oscillator (17) as a reference clock and has at least two separate channels arranged to sample and convert input data at two differing clock rates. Each channel derives a clock signal from the reference clock. Associated with each of the channels is a Sigma-Delta converter (10a, 10b) comprising a modulator (12), a filter (14) and a resampler (18). The modulator (12) receives input data and provides a data signal to the filter (14), which itself provides a filtered data signal to the associated data resampler. The data resampler resamples the data and provides a digital output signal. As there is sampling in the digital domain the advantages associated with signal processing, speed and low noise injection are obtained. Similarly as the output of the modulator (12) is in digital form, it can be manipulated and processed readily and with existing software.

摘要翻译： 多速率模数转换器（19）耦合到作为参考时钟的单晶振荡器（17），并且具有至少两个单独的通道，其布置成以两个不同的时钟速率对输入数据进行采样和转换。 每个通道从参考时钟导出时钟信号。 与每个通道相关联的是包括调制器（12），滤波器（14）和重采样器（18）的Σ-Δ转换器（10a，10b）。 调制器（12）接收输入数据并向滤波器（14）提供数据信号，滤波器本身将经过滤波的数据信号提供给相关联的数据重采样器。 数据重采样器重新采样数据并提供数字输出信号。 由于在数字领域中采用了与信号处理，速度和低噪声注入相关的优点。 类似地，当调制器（12）的输出是数字形式时，可以容易地和现有的软件操纵和处理调制器（12）的输出。

公开(公告)号：US07672689B2

公开(公告)日：2010-03-02

申请号：US10433855

申请日：2001-10-22

申请人： Nadim Khlat ,  Patrick Clement

发明人： Nadim Khlat ,  Patrick Clement

IPC分类号： H04M1/00

CPC分类号： H04B1/7115 ,  H04B1/30 ,  H04B1/406

摘要： A multipath wideband communications receiver (100) having a plurality of RF signal paths (116, 136) covering different but overlapping frequency bands and a plurality of baseband signal paths (140, 150, 160, 170, 180, 190), the paths being re-configurable for sharing of the first and second paths in different ways in order to facilitate processing of received signals in different modes.Also, a rake receiver (800) employs a sigma-delta modulator arrangement (810) and programmable delays to provide fine delay adjustment. The sigma-delta modulator (810) may use sigma-delta circuitry from a sigma-delta A/D converters in a baseband paths of the receiver (100), that this may be achieved with no loss of functionality if in a particular reception configuration that sigma-delta A/D converter is not being utilized.

摘要翻译： 多径宽带通信接收机（100）具有覆盖不同但重叠的频带的多个RF信号路径（116,136）和多个基带信号路径（140,150,160,170,180,190），所述路径是 可重新配置为以不同方式共享第一和第二路径，以便于以不同模式处理接收到的信号。 此外，瑞克接收机（800）采用Σ-Δ调制器装置（810）和可编程延迟来提供精细的延迟调整。 Σ-Δ调制器（810）可以在接收机（100）的基带路径中使用来自Σ-ΔA/ D转换器的Σ-Δ电路，如果在特定的接收配置中可以实现这一点，而不损失功能 该Σ-ΔA / D转换器未被使用。

公开(公告)号：US07190293B2

公开(公告)日：2007-03-13

申请号：US10515561

申请日：2003-05-19

申请人： Patrick Clement ,  Nadim Khlat

发明人： Patrick Clement ,  Nadim Khlat

IPC分类号： H03M1/12

CPC分类号： H03M3/466 ,  H03M3/41

摘要： An arrangement (100) and method for sigma-delta analog-to-digital conversion by providing parallel translating sigma-delta analog-to-digital converters (21, 22) and summing their outputs to produce a digital output signal having a bandwidth greater than that of the first or second translating sigma-delta analog-to-digital converters (21, 22). The parallel translating sigma-delta analog-to-digital converters (21, 22) use switching sequences arranged to cancel third and fifth harmonics in the digital output signal. Orthogonality error in the switching sequences applied to the sigma-delta modulators is compensated by adjusting the phase of the signals applied to mixers (51, 52).

摘要翻译： 一种用于通过提供并行转换Σ-Δ模数转换器（21,22）并对其输出进行求和以产生具有大于或等于的带宽的数字输出信号的Σ-Δ模数转换的装置（100）和方法 第一或第二平移Σ-Δ模数转换器（21,22）的转换。 并行转换Σ-Δ模数转换器（21,22）使用布置成消除数字输出信号中的第三和第五谐波的开关序列。 通过调整施加到混合器（51,52）的信号的相位来补偿施加到Σ-Δ调制器的开关序列中的正交性误差。

公开(公告)号：US20120180924A1

公开(公告)日：2012-07-19

申请号：US13392812

申请日：2010-09-03

申请人： Stéphane Auvray ,  Eric Carpentier ,  Patrick Clement

发明人： Stéphane Auvray ,  Eric Carpentier ,  Patrick Clement

IPC分类号： B60C17/04 ,  B23P11/02

CPC分类号： B60C17/06 ,  B60C2017/068 ,  Y10T29/49492

摘要： The present invention relates to a flat-running device intended for being fitted on an assembly mounted on a tubeless one-piece rim for an automobile, said mounted assembly including said device, and to a method for mounting and/or removing said mounted assembly. The device according to the invention (1) includes a ring (2) with a radially internal mounting surface for the device, intended to closely match the hollow section of the rim (11), the ring having an open structure with two ends held closely facing one another by a means (5) for clamping the ring. According to the invention, at least one transverse notch (6), the two edges and the bottom of which are located under one of the ends of the ring, is formed in at least one of said side portions (3a), forming a circumferential lip which projects axially from the corresponding side wall of the ring, which includes said recess and is suitable for wedging the ring in the hollow section of the rim, such as to enable, via said notch, transverse insertion of a tool (7) such as a lever between the rim and said mounting surface in order to facilitate the operations of mounting and/or removing the device on the rim.

摘要翻译： 本发明涉及一种用于安装在安装在用于汽车的无内胎一体式轮辋上的组件上的平行装置，所述安装组件包括所述装置，以及用于安装和/或移除所述安装组件的方法。 根据本发明的装置（1）包括具有用于装置的径向内部安装表面的环（2），用于紧密地匹配轮辋（11）的中空部分，所述环具有开口结构，其两端紧密地保持 通过用于夹紧环的装置（5）彼此面对。 根据本发明，至少一个横向切口（6），其两个边缘和底部位于环的一个端部下方，形成在至少一个所述侧部（3a）中，形成周向 所述唇部从所述环的相应侧壁轴向突出，所述唇部包括所述凹部并且适于将所述环楔入所述边缘的中空部分，以便经由所述切口能够横向插入工具（7） 作为在边缘和所述安装表面之间的杠杆，以便于在边缘上安装和/或移除装置的操作。

公开(公告)号：US07953382B1

公开(公告)日：2011-05-31

申请号：US11970443

申请日：2008-01-07

申请人： Patrick Clement ,  Lydi Smaini ,  Pantas Sutardja

发明人： Patrick Clement ,  Lydi Smaini ,  Pantas Sutardja

IPC分类号： H04B7/08

CPC分类号： H04B1/034

摘要： Methods and apparatuses for quiet spot detection for radio frequency transmission thereon. According to various embodiments, a device may include a local receiver configured to evaluate one or more frequencies of a frequency band to determine a quiet spot frequency, the device further including a local transmitter configured to transmit signals at the quiet spot frequency.

摘要翻译： 用于无线电频率传输的安静点检测的方法和装置。 根据各种实施例，设备可以包括被配置为评估频带的一个或多个频率以确定安静点频率的本地接收机，该设备还包括被配置为以安静点频率发射信号的本地发射机。