公开(公告)号：US07462542B2

公开(公告)日：2008-12-09

申请号：US11936093

申请日：2007-11-07

申请人： Alex Liu ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

发明人： Alex Liu ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

IPC分类号： H01L21/8234

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845 ,  Y10S438/938

摘要： A method of fabricating semiconductor devices is provided. A plurality of gate structures is formed over a substrate. A source region and a drain region are formed in the substrate and adjacent to sidewalls of each gate structure. A self-aligned salicide block (SAB) layer is formed over the substrate to cover the gate structures and the exposed surface of the substrate. An anneal process is performed. The SAB layer creates a tension stress during the anneal process so that the substrate under the gate structures is subjected to the tension stress. A portion of the SAB layer is removed to expose a portion of the gate structures and a portion of the surface of the substrate. A salicide process is performed.

摘要翻译： 提供一种制造半导体器件的方法。 在衬底上形成多个栅极结构。 源极区域和漏极区域形成在衬底中并且邻近每个栅极结构的侧壁。 在衬底上形成自对准的自对准硅化物块（SAB）层以覆盖栅极结构和衬底的暴露表面。 进行退火处理。 SAB层在退火过程中产生拉伸应力，使得栅极结构下的基板受到张力应力。 去除SAB层的一部分以暴露栅极结构的一部分和衬底表面的一部分。 执行自杀化合物处理。

公开(公告)号：US20080057655A1

公开(公告)日：2008-03-06

申请号：US11936093

申请日：2007-11-07

申请人： Alex Liu ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

发明人： Alex Liu ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

IPC分类号： H01L21/336

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845 ,  Y10S438/938

摘要： A method of fabricating semiconductor devices is provided. A plurality of gate structures is formed over a substrate. A source region and a drain region are formed in the substrate and adjacent to sidewalls of each gate structure. A self-aligned salicide block (SAB) layer is formed over the substrate to cover the gate structures and the exposed surface of the substrate. An anneal process is performed. The SAB layer creates a tension stress during the anneal process so that the substrate under the gate structures is subjected to the tension stress. A portion of the SAB layer is removed to expose a portion of the gate structures and a portion of the surface of the substrate. A salicide process is performed.

摘要翻译： 提供一种制造半导体器件的方法。 在衬底上形成多个栅极结构。 源极区域和漏极区域形成在衬底中并且邻近每个栅极结构的侧壁。 在衬底上形成自对准的自对准硅化物块（SAB）层以覆盖栅极结构和衬底的暴露表面。 进行退火处理。 SAB层在退火过程中产生拉伸应力，使得栅极结构下的基板受到张力应力。 去除SAB层的一部分以暴露栅极结构的一部分和衬底表面的一部分。 执行自杀化合物处理。

公开(公告)号：US20060228843A1

公开(公告)日：2006-10-12

申请号：US10907677

申请日：2005-04-12

申请人： Alex Liu ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

发明人： Alex Liu ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845 ,  Y10S438/938

摘要： A method of fabricating semiconductor devices is provided. A plurality of gate structures is formed over a substrate. A source region and a drain region are formed in the substrate and adjacent to sidewalls of each gate structure. A self-aligned salicide block (SAB) layer is formed over the substrate to cover the gate structures and the exposed surface of the substrate. An anneal process is performed. The SAB layer creates a tension stress during the anneal process so that the substrate under the gate structures is subjected to the tension stress. A portion of the SAB layer is removed to expose a portion of the gate structures and a portion of the surface of the substrate. A salicide process is performed.

摘要翻译： 提供一种制造半导体器件的方法。 在衬底上形成多个栅极结构。 源极区域和漏极区域形成在衬底中并且邻近每个栅极结构的侧壁。 在衬底上形成自对准的自对准硅化物块（SAB）层以覆盖栅极结构和衬底的暴露表面。 进行退火处理。 SAB层在退火过程中产生拉伸应力，使得栅极结构下的基板受到张力应力。 去除SAB层的一部分以暴露栅极结构的一部分和衬底表面的一部分。 执行自杀化合物处理。

公开(公告)号：US07326622B2

公开(公告)日：2008-02-05

申请号：US11164031

申请日：2005-11-08

申请人： Yi-Cheng Liu ,  Jiunn-Ren Hwang ,  Wei-Tsun Shiau ,  Cheng-Tung Huang ,  Kuan-Yang Liao

发明人： Yi-Cheng Liu ,  Jiunn-Ren Hwang ,  Wei-Tsun Shiau ,  Cheng-Tung Huang ,  Kuan-Yang Liao

IPC分类号： H01L21/336

CPC分类号： H01L29/7843 ,  H01L21/265 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate having a main surface is prepared. A gate dielectric layer is formed on the main surface. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A silicon nitride spacer is formed on the liner. The main surface is then ion implanted using the gate electrode and the silicon nitride spacer as an implantation mask, thereby forming a source/drain region of the MOS transistor device in the main surface. The silicon nitride spacer is removed. A silicon nitride cap layer that borders the liner is deposited. The silicon nitride cap layer has a specific stress status.

摘要翻译： 公开了一种制造金属氧化物半导体（MOS）晶体管器件的方法。 制备具有主表面的半导体衬底。 在主表面上形成栅介质层。 在栅极电介质层上形成栅电极。 栅电极具有垂直侧壁和顶表面。 衬套形成在栅电极的垂直侧壁上。 在衬套上形成氮化硅衬垫。 然后使用栅电极和氮化硅间隔物作为注入掩模离子注入主表面，从而在主表面形成MOS晶体管器件的源/漏区。 去除氮化硅间隔物。 与衬垫相邻的氮化硅覆盖层被沉积。 氮化硅盖层具有特定的应力状态。

公开(公告)号：US20060094195A1

公开(公告)日：2006-05-04

申请号：US11164031

申请日：2005-11-08

申请人： Yi-Cheng Liu ,  Jiunn-Ren Hwang ,  Wei-Tsun Shiau ,  Cheng-Tung Huang ,  Kuan-Yang Liao

发明人： Yi-Cheng Liu ,  Jiunn-Ren Hwang ,  Wei-Tsun Shiau ,  Cheng-Tung Huang ,  Kuan-Yang Liao

IPC分类号： H01L21/336

CPC分类号： H01L29/7843 ,  H01L21/265 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate having a main surface is prepared. A gate dielectric layer is formed on the main surface. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A silicon nitride spacer is formed on the liner. The main surface is then ion implanted using the gate electrode and the silicon nitride spacer as an implantation mask, thereby forming a source/drain region of the MOS transistor device in the main surface. The silicon nitride spacer is removed. A silicon nitride cap layer that borders the liner is deposited. The silicon nitride cap layer has a specific stress status.

摘要翻译： 公开了一种制造金属氧化物半导体（MOS）晶体管器件的方法。 制备具有主表面的半导体衬底。 在主表面上形成栅介质层。 在栅极电介质层上形成栅电极。 栅电极具有垂直侧壁和顶表面。 衬套形成在栅电极的垂直侧壁上。 在衬套上形成氮化硅衬垫。 然后使用栅电极和氮化硅间隔物作为注入掩模离子注入主表面，从而在主表面形成MOS晶体管器件的源/漏区。 去除氮化硅间隔物。 与衬垫相邻的氮化硅覆盖层被沉积。 氮化硅盖层具有特定的应力状态。

公开(公告)号：US07135365B2

公开(公告)日：2006-11-14

申请号：US10907342

申请日：2005-03-30

申请人： Yi-Cheng Liu ,  Wen-Chi Chen ,  Tzu-Yun Chang ,  Bang-Chiang Lan ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

发明人： Yi-Cheng Liu ,  Wen-Chi Chen ,  Tzu-Yun Chang ,  Bang-Chiang Lan ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823864 ,  H01L21/823807 ,  H01L21/823814

摘要： First, a substrate having a plurality of NMOS transistor regions and PMOS transistor regions is provided. The substrate further includes a plurality of gate structures respectively positioned in the NMOS transistor regions and the PMOS transistor regions. A high-tensile thin film is then formed on the substrate and the plurality of gate structures. Subsequently, an annealing process is performed, and the high-tensile thin film is removed after the annealing process.

摘要翻译： 首先，提供具有多个NMOS晶体管区域和PMOS晶体管区域的衬底。 衬底还包括分别位于NMOS晶体管区域和PMOS晶体管区域中的多个栅极结构。 然后在基板和多个栅极结构上形成高拉伸薄膜。 随后，进行退火处理，并且在退火处理之后去除高拉伸薄膜。

公开(公告)号：US20060099763A1

公开(公告)日：2006-05-11

申请号：US10904210

申请日：2004-10-28

申请人： Yi-Cheng Liu ,  Jiunn-Ren Hwang ,  Wei-Tsun Shiau ,  Cheng-Tung Huang ,  Kuan-Yang Liao

发明人： Yi-Cheng Liu ,  Jiunn-Ren Hwang ,  Wei-Tsun Shiau ,  Cheng-Tung Huang ,  Kuan-Yang Liao

IPC分类号： H01L21/336

CPC分类号： H01L29/7843 ,  H01L21/265 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate having a main surface is prepared. A gate dielectric layer is formed on the main surface. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A silicon nitride spacer is formed on the liner. The main surface is then ion implanted using the gate electrode and the silicon nitride spacer as an implantation mask, thereby forming a source/drain region of the MOS transistor device in the main surface. The silicon nitride spacer is removed. A silicon nitride cap layer that borders the liner is deposited. The silicon nitride cap layer has a specific stress status.

公开(公告)号：US20060228847A1

公开(公告)日：2006-10-12

申请号：US10907342

申请日：2005-03-30

申请人： Yi-Cheng Liu ,  Wen-Chi Chen ,  Tzu-Yun Chang ,  Bang-Chiang Lan ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

发明人： Yi-Cheng Liu ,  Wen-Chi Chen ,  Tzu-Yun Chang ,  Bang-Chiang Lan ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823864 ,  H01L21/823807 ,  H01L21/823814

摘要： First, a substrate having a plurality of NMOS transistor regions and PMOS transistor regions is provided. The substrate further includes a plurality of gate structures respectively positioned in the NMOS transistor regions and the PMOS transistor regions. A high-tensile thin film is then formed on the substrate and the plurality of gate structures. Subsequently, an annealing process is performed, and the high-tensile thin film is removed after the annealing process.

摘要翻译： 首先，提供具有多个NMOS晶体管区域和PMOS晶体管区域的衬底。 衬底还包括分别位于NMOS晶体管区域和PMOS晶体管区域中的多个栅极结构。 然后在基板和多个栅极结构上形成高拉伸薄膜。 随后，进行退火处理，并且在退火处理之后去除高拉伸薄膜。

公开(公告)号：US20120199890A1

公开(公告)日：2012-08-09

申请号：US13450444

申请日：2012-04-18

申请人： Wen-Han Hung ,  Tsai-Fu Chen ,  Shyh-Fann Ting ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Ta-Kang Lo ,  Tzyy-Ming Cheng

发明人： Wen-Han Hung ,  Tsai-Fu Chen ,  Shyh-Fann Ting ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Ta-Kang Lo ,  Tzyy-Ming Cheng

IPC分类号： H01L29/78

CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7848

摘要： A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a P-type well, a gate disposed on the P-type well, a first spacer disposed on the gate, an N-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the N-type source/drain region, a second spacer around the first spacer and the second spacer directly on and covering a portion of the silicon cap layer and a silicide layer disposed on the silicon cap layer.

摘要翻译： 在本发明中提供一种晶体管结构。 晶体管结构包括：包括P型阱的衬底，设置在P型阱上的栅极，设置在栅极上的第一间隔物，设置在栅极两侧的衬底中的N型源极/漏极区域 覆盖N型源极/漏极区域的硅覆盖层，围绕第一间隔物的第二间隔物和第二间隔物，直接覆盖硅覆盖层的一部分并且覆盖硅覆盖层上的硅化物层。

公开(公告)号：US07928512B2

公开(公告)日：2011-04-19

申请号：US11776562

申请日：2007-07-12

申请人： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Tzyy-Ming Cheng ,  Chia-Wen Lang

发明人： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Tzyy-Ming Cheng ,  Chia-Wen Lang

IPC分类号： H01L27/12

CPC分类号： H01L21/823412 ,  H01L21/823468 ,  H01L29/7842

摘要： A semiconductor device is provided herein, which includes a substrate having a first-type MOS transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor formed thereon. The semiconductor device further includes a first stress layer and a second stress layer. The first stress layer is disposed on the first-type MOS transistor, or on the first-type MOS transistor and the I/O second-type MOS transistor. The second stress layer is disposed on the core second-type MOS transistor.

摘要翻译： 本文提供了一种半导体器件，其包括具有第一型MOS晶体管，形成在其上的输入/输出（I / O）第二型MOS晶体管和核心第二型MOS晶体管的衬底。 半导体器件还包括第一应力层和第二应力层。 第一应力层设置在第一型MOS晶体管上或第一型MOS晶体管和I / O第二型MOS晶体管上。 第二应力层设置在芯型二次型MOS晶体管上。