公开(公告)号：US20060099763A1

公开(公告)日：2006-05-11

申请号：US10904210

申请日：2004-10-28

申请人： Yi-Cheng Liu ,  Jiunn-Ren Hwang ,  Wei-Tsun Shiau ,  Cheng-Tung Huang ,  Kuan-Yang Liao

发明人： Yi-Cheng Liu ,  Jiunn-Ren Hwang ,  Wei-Tsun Shiau ,  Cheng-Tung Huang ,  Kuan-Yang Liao

IPC分类号： H01L21/336

CPC分类号： H01L29/7843 ,  H01L21/265 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate having a main surface is prepared. A gate dielectric layer is formed on the main surface. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A silicon nitride spacer is formed on the liner. The main surface is then ion implanted using the gate electrode and the silicon nitride spacer as an implantation mask, thereby forming a source/drain region of the MOS transistor device in the main surface. The silicon nitride spacer is removed. A silicon nitride cap layer that borders the liner is deposited. The silicon nitride cap layer has a specific stress status.

公开(公告)号：US07326622B2

公开(公告)日：2008-02-05

申请号：US11164031

申请日：2005-11-08

申请人： Yi-Cheng Liu ,  Jiunn-Ren Hwang ,  Wei-Tsun Shiau ,  Cheng-Tung Huang ,  Kuan-Yang Liao

发明人： Yi-Cheng Liu ,  Jiunn-Ren Hwang ,  Wei-Tsun Shiau ,  Cheng-Tung Huang ,  Kuan-Yang Liao

IPC分类号： H01L21/336

CPC分类号： H01L29/7843 ,  H01L21/265 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate having a main surface is prepared. A gate dielectric layer is formed on the main surface. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A silicon nitride spacer is formed on the liner. The main surface is then ion implanted using the gate electrode and the silicon nitride spacer as an implantation mask, thereby forming a source/drain region of the MOS transistor device in the main surface. The silicon nitride spacer is removed. A silicon nitride cap layer that borders the liner is deposited. The silicon nitride cap layer has a specific stress status.

摘要翻译： 公开了一种制造金属氧化物半导体（MOS）晶体管器件的方法。 制备具有主表面的半导体衬底。 在主表面上形成栅介质层。 在栅极电介质层上形成栅电极。 栅电极具有垂直侧壁和顶表面。 衬套形成在栅电极的垂直侧壁上。 在衬套上形成氮化硅衬垫。 然后使用栅电极和氮化硅间隔物作为注入掩模离子注入主表面，从而在主表面形成MOS晶体管器件的源/漏区。 去除氮化硅间隔物。 与衬垫相邻的氮化硅覆盖层被沉积。 氮化硅盖层具有特定的应力状态。

公开(公告)号：US20060094195A1

公开(公告)日：2006-05-04

申请号：US11164031

申请日：2005-11-08

申请人： Yi-Cheng Liu ,  Jiunn-Ren Hwang ,  Wei-Tsun Shiau ,  Cheng-Tung Huang ,  Kuan-Yang Liao

发明人： Yi-Cheng Liu ,  Jiunn-Ren Hwang ,  Wei-Tsun Shiau ,  Cheng-Tung Huang ,  Kuan-Yang Liao

IPC分类号： H01L21/336

CPC分类号： H01L29/7843 ,  H01L21/265 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate having a main surface is prepared. A gate dielectric layer is formed on the main surface. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A silicon nitride spacer is formed on the liner. The main surface is then ion implanted using the gate electrode and the silicon nitride spacer as an implantation mask, thereby forming a source/drain region of the MOS transistor device in the main surface. The silicon nitride spacer is removed. A silicon nitride cap layer that borders the liner is deposited. The silicon nitride cap layer has a specific stress status.

摘要翻译： 公开了一种制造金属氧化物半导体（MOS）晶体管器件的方法。 制备具有主表面的半导体衬底。 在主表面上形成栅介质层。 在栅极电介质层上形成栅电极。 栅电极具有垂直侧壁和顶表面。 衬套形成在栅电极的垂直侧壁上。 在衬套上形成氮化硅衬垫。 然后使用栅电极和氮化硅间隔物作为注入掩模离子注入主表面，从而在主表面形成MOS晶体管器件的源/漏区。 去除氮化硅间隔物。 与衬垫相邻的氮化硅覆盖层被沉积。 氮化硅盖层具有特定的应力状态。

公开(公告)号：US07135365B2

公开(公告)日：2006-11-14

申请号：US10907342

申请日：2005-03-30

申请人： Yi-Cheng Liu ,  Wen-Chi Chen ,  Tzu-Yun Chang ,  Bang-Chiang Lan ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

发明人： Yi-Cheng Liu ,  Wen-Chi Chen ,  Tzu-Yun Chang ,  Bang-Chiang Lan ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823864 ,  H01L21/823807 ,  H01L21/823814

摘要： First, a substrate having a plurality of NMOS transistor regions and PMOS transistor regions is provided. The substrate further includes a plurality of gate structures respectively positioned in the NMOS transistor regions and the PMOS transistor regions. A high-tensile thin film is then formed on the substrate and the plurality of gate structures. Subsequently, an annealing process is performed, and the high-tensile thin film is removed after the annealing process.

摘要翻译： 首先，提供具有多个NMOS晶体管区域和PMOS晶体管区域的衬底。 衬底还包括分别位于NMOS晶体管区域和PMOS晶体管区域中的多个栅极结构。 然后在基板和多个栅极结构上形成高拉伸薄膜。 随后，进行退火处理，并且在退火处理之后去除高拉伸薄膜。

公开(公告)号：US20060228847A1

公开(公告)日：2006-10-12

申请号：US10907342

申请日：2005-03-30

申请人： Yi-Cheng Liu ,  Wen-Chi Chen ,  Tzu-Yun Chang ,  Bang-Chiang Lan ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

发明人： Yi-Cheng Liu ,  Wen-Chi Chen ,  Tzu-Yun Chang ,  Bang-Chiang Lan ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823864 ,  H01L21/823807 ,  H01L21/823814

摘要： First, a substrate having a plurality of NMOS transistor regions and PMOS transistor regions is provided. The substrate further includes a plurality of gate structures respectively positioned in the NMOS transistor regions and the PMOS transistor regions. A high-tensile thin film is then formed on the substrate and the plurality of gate structures. Subsequently, an annealing process is performed, and the high-tensile thin film is removed after the annealing process.

摘要翻译： 首先，提供具有多个NMOS晶体管区域和PMOS晶体管区域的衬底。 衬底还包括分别位于NMOS晶体管区域和PMOS晶体管区域中的多个栅极结构。 然后在基板和多个栅极结构上形成高拉伸薄膜。 随后，进行退火处理，并且在退火处理之后去除高拉伸薄膜。

公开(公告)号：US20080057655A1

公开(公告)日：2008-03-06

申请号：US11936093

申请日：2007-11-07

申请人： Alex Liu ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

发明人： Alex Liu ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

IPC分类号： H01L21/336

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845 ,  Y10S438/938

摘要： A method of fabricating semiconductor devices is provided. A plurality of gate structures is formed over a substrate. A source region and a drain region are formed in the substrate and adjacent to sidewalls of each gate structure. A self-aligned salicide block (SAB) layer is formed over the substrate to cover the gate structures and the exposed surface of the substrate. An anneal process is performed. The SAB layer creates a tension stress during the anneal process so that the substrate under the gate structures is subjected to the tension stress. A portion of the SAB layer is removed to expose a portion of the gate structures and a portion of the surface of the substrate. A salicide process is performed.

摘要翻译： 提供一种制造半导体器件的方法。 在衬底上形成多个栅极结构。 源极区域和漏极区域形成在衬底中并且邻近每个栅极结构的侧壁。 在衬底上形成自对准的自对准硅化物块（SAB）层以覆盖栅极结构和衬底的暴露表面。 进行退火处理。 SAB层在退火过程中产生拉伸应力，使得栅极结构下的基板受到张力应力。 去除SAB层的一部分以暴露栅极结构的一部分和衬底表面的一部分。 执行自杀化合物处理。

公开(公告)号：US07462542B2

公开(公告)日：2008-12-09

申请号：US11936093

申请日：2007-11-07

申请人： Alex Liu ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

发明人： Alex Liu ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

IPC分类号： H01L21/8234

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845 ,  Y10S438/938

摘要： A method of fabricating semiconductor devices is provided. A plurality of gate structures is formed over a substrate. A source region and a drain region are formed in the substrate and adjacent to sidewalls of each gate structure. A self-aligned salicide block (SAB) layer is formed over the substrate to cover the gate structures and the exposed surface of the substrate. An anneal process is performed. The SAB layer creates a tension stress during the anneal process so that the substrate under the gate structures is subjected to the tension stress. A portion of the SAB layer is removed to expose a portion of the gate structures and a portion of the surface of the substrate. A salicide process is performed.

摘要翻译： 提供一种制造半导体器件的方法。 在衬底上形成多个栅极结构。 源极区域和漏极区域形成在衬底中并且邻近每个栅极结构的侧壁。 在衬底上形成自对准的自对准硅化物块（SAB）层以覆盖栅极结构和衬底的暴露表面。 进行退火处理。 SAB层在退火过程中产生拉伸应力，使得栅极结构下的基板受到张力应力。 去除SAB层的一部分以暴露栅极结构的一部分和衬底表面的一部分。 执行自杀化合物处理。

公开(公告)号：US20060228843A1

公开(公告)日：2006-10-12

申请号：US10907677

申请日：2005-04-12

申请人： Alex Liu ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

发明人： Alex Liu ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845 ,  Y10S438/938

摘要： A method of fabricating semiconductor devices is provided. A plurality of gate structures is formed over a substrate. A source region and a drain region are formed in the substrate and adjacent to sidewalls of each gate structure. A self-aligned salicide block (SAB) layer is formed over the substrate to cover the gate structures and the exposed surface of the substrate. An anneal process is performed. The SAB layer creates a tension stress during the anneal process so that the substrate under the gate structures is subjected to the tension stress. A portion of the SAB layer is removed to expose a portion of the gate structures and a portion of the surface of the substrate. A salicide process is performed.

摘要翻译： 提供一种制造半导体器件的方法。 在衬底上形成多个栅极结构。 源极区域和漏极区域形成在衬底中并且邻近每个栅极结构的侧壁。 在衬底上形成自对准的自对准硅化物块（SAB）层以覆盖栅极结构和衬底的暴露表面。 进行退火处理。 SAB层在退火过程中产生拉伸应力，使得栅极结构下的基板受到张力应力。 去除SAB层的一部分以暴露栅极结构的一部分和衬底表面的一部分。 执行自杀化合物处理。

公开(公告)号：US20060172476A1

公开(公告)日：2006-08-03

申请号：US11049819

申请日：2005-02-02

申请人： Wen-Shiang Liao ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

发明人： Wen-Shiang Liao ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8242

CPC分类号： H01L29/66795 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/66507 ,  H01L29/785

摘要： The invention is directed to a method for manufacturing a fin field effect transistor including a fully silicidated gate electrode. The method is suitable for a substrate including a fin structure, a straddle gate, a source/drain region and a dielectric layer formed thereon, wherein the straddle gate straddles over the fin structure, the source/drain region is located in a portion of the fin structure exposed by the straddle gate and the dielectric layer covers the substrate. The method includes steps of performing a planarization process to remove a portion of the dielectric layer and the first salicide layer until the surface of the straddle gate is exposed and performing a salicide process to convert the straddle gate into a fully silicidated gate electrode.

摘要翻译： 本发明涉及一种制造包括完全硅化栅电极的鳍式场效应晶体管的方法。 该方法适用于包括翅片结构，跨骑栅极，源极/漏极区域和形成在其上的电介质层的衬底，其中跨越栅极跨过鳍状结构，源极/漏极区域位于 通过跨门和电介质层暴露的翅片结构覆盖基板。 该方法包括以下步骤：执行平坦化处理以去除电介质层和第一自对准硅化物层的一部分，直到暴露了跨越栅极的表面，并执行自对准硅化处理以将跨门转换成完全硅化的栅电极。

公开(公告)号：US20070126032A1

公开(公告)日：2007-06-07

申请号：US11673767

申请日：2007-02-12

申请人： WEN-SHIANG LIAO ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

发明人： WEN-SHIANG LIAO ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

IPC分类号： H01L29/76

CPC分类号： H01L29/66795 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/66507 ,  H01L29/785

摘要： The invention is directed to a method for manufacturing a fin field effect transistor including a fully silicidated gate electrode. The method is suitable for a substrate including a fin structure, a straddle gate, a source/drain region and a dielectric layer formed thereon, wherein the straddle gate straddles over the fin structure, the source/drain region is located in a portion of the fin structure exposed by the straddle gate and the dielectric layer covers the substrate. The method includes steps of performing a planarization process to remove a portion of the dielectric layer and the first salicide layer until the surface of the straddle gate is exposed and performing a salicide process to convert the straddle gate into a fully silicidated gate electrode.

摘要翻译： 本发明涉及一种制造包括完全硅化栅电极的鳍式场效应晶体管的方法。 该方法适用于包括翅片结构，跨骑栅极，源极/漏极区域和形成在其上的电介质层的衬底，其中跨越栅极跨过鳍状结构，源极/漏极区域位于 通过跨门和电介质层暴露的翅片结构覆盖基板。 该方法包括以下步骤：执行平坦化处理以去除电介质层和第一自对准硅化物层的一部分，直到暴露了跨越栅极的表面，并执行自对准硅化处理以将跨门转换成完全硅化的栅电极。