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    Method of manufacturing semiconductor MOS transistor device
    2.
    发明授权
    Method of manufacturing semiconductor MOS transistor device 有权
    制造半导体MOS晶体管器件的方法

    公开(公告)号：US07326622B2

    公开(公告)日：2008-02-05

    申请号：US11164031

    申请日：2005-11-08

    申请人： Yi-Cheng Liu ,  Jiunn-Ren Hwang ,  Wei-Tsun Shiau ,  Cheng-Tung Huang ,  Kuan-Yang Liao

    发明人： Yi-Cheng Liu ,  Jiunn-Ren Hwang ,  Wei-Tsun Shiau ,  Cheng-Tung Huang ,  Kuan-Yang Liao

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7843 ,  H01L21/265 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

    摘要： A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate having a main surface is prepared. A gate dielectric layer is formed on the main surface. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A silicon nitride spacer is formed on the liner. The main surface is then ion implanted using the gate electrode and the silicon nitride spacer as an implantation mask, thereby forming a source/drain region of the MOS transistor device in the main surface. The silicon nitride spacer is removed. A silicon nitride cap layer that borders the liner is deposited. The silicon nitride cap layer has a specific stress status.

    摘要翻译： 公开了一种制造金属氧化物半导体（MOS）晶体管器件的方法。 制备具有主表面的半导体衬底。 在主表面上形成栅介质层。 在栅极电介质层上形成栅电极。 栅电极具有垂直侧壁和顶表面。 衬套形成在栅电极的垂直侧壁上。 在衬套上形成氮化硅衬垫。 然后使用栅电极和氮化硅间隔物作为注入掩模离子注入主表面，从而在主表面形成MOS晶体管器件的源/漏区。 去除氮化硅间隔物。 与衬垫相邻的氮化硅覆盖层被沉积。 氮化硅盖层具有特定的应力状态。

    METHOD OF MANUFACTURING SEMICONDUCTOR MOS TRANSISTOR DEVICE
    3.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR MOS TRANSISTOR DEVICE 有权
    制造半导体MOS晶体管器件的方法

    公开(公告)号：US20060094195A1

    公开(公告)日：2006-05-04

    申请号：US11164031

    申请日：2005-11-08

    申请人： Yi-Cheng Liu ,  Jiunn-Ren Hwang ,  Wei-Tsun Shiau ,  Cheng-Tung Huang ,  Kuan-Yang Liao

    发明人： Yi-Cheng Liu ,  Jiunn-Ren Hwang ,  Wei-Tsun Shiau ,  Cheng-Tung Huang ,  Kuan-Yang Liao

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7843 ,  H01L21/265 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

    摘要： A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate having a main surface is prepared. A gate dielectric layer is formed on the main surface. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A silicon nitride spacer is formed on the liner. The main surface is then ion implanted using the gate electrode and the silicon nitride spacer as an implantation mask, thereby forming a source/drain region of the MOS transistor device in the main surface. The silicon nitride spacer is removed. A silicon nitride cap layer that borders the liner is deposited. The silicon nitride cap layer has a specific stress status.

    摘要翻译： 公开了一种制造金属氧化物半导体（MOS）晶体管器件的方法。 制备具有主表面的半导体衬底。 在主表面上形成栅介质层。 在栅极电介质层上形成栅电极。 栅电极具有垂直侧壁和顶表面。 衬套形成在栅电极的垂直侧壁上。 在衬套上形成氮化硅衬垫。 然后使用栅电极和氮化硅间隔物作为注入掩模离子注入主表面，从而在主表面形成MOS晶体管器件的源/漏区。 去除氮化硅间隔物。 与衬垫相邻的氮化硅覆盖层被沉积。 氮化硅盖层具有特定的应力状态。

    Semiconductor structure and method for forming thereof
    6.
    发明申请
    Semiconductor structure and method for forming thereof 审中-公开
    半导体结构及其形成方法

    公开(公告)号：US20060286730A1

    公开(公告)日：2006-12-21

    申请号：US11154377

    申请日：2005-06-15

    申请人： Yi-Cheng Liu (Alex Liu) ,  Jiunn-Ren Hwang ,  Wei-Tsun Shiau

    发明人： Yi-Cheng Liu (Alex Liu) ,  Jiunn-Ren Hwang ,  Wei-Tsun Shiau

    IPC分类号： H01L21/8234 ,  H01L21/336

    CPC分类号： H01L29/7848 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

    摘要： A semiconductor structure and a method for forming the semiconductor structure are provided. The method for forming a semiconductor structure of the present invention may include the following steps. First, a substrate is provided, wherein a gate is formed over the substrate, and a plurality of offspacers are formed over a sidewall of the gate. Then, a source/drain trench is formed in the substrate at two sides of the gate respectively. Next, an outermost offspacer of the offspacers is removed to expose a flat surface on a surface of the substrate. Thereafter, the source/drain trenches are filled to form a source/drain region. Then, a lightly doped drain (LDD) region is formed in a portion of the substrate under the flat surface.

    摘要翻译： 提供半导体结构和形成半导体结构的方法。 本发明的半导体结构的形成方法可以包括以下步骤。 首先，提供衬底，其中在衬底上形成栅极，并且在栅极的侧壁上方形成多个脱离层。 然后，在栅极的两侧分别在衬底中形成源极/漏极沟槽。 接下来，除去离子的最外层的隔离物以露出基底表面上的平坦表面。 此后，填充源极/漏极沟槽以形成源极/漏极区域。 然后，在平坦表面下的基板的一部分中形成轻掺杂漏极（LDD）区域。

    METHOD OF FABRICATING SEMICONDUCTOR DEVICES AND METHOD OF ADJUSTING LATTICE DISTANCE IN DEVICE CHANNEL
    7.
    发明申请
    METHOD OF FABRICATING SEMICONDUCTOR DEVICES AND METHOD OF ADJUSTING LATTICE DISTANCE IN DEVICE CHANNEL 有权
    制造半导体器件的方法和调整器件通道中的晶体距离的方法

    公开(公告)号：US20080057655A1

    公开(公告)日：2008-03-06

    申请号：US11936093

    申请日：2007-11-07

    申请人： Alex Liu ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

    发明人： Alex Liu ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845 ,  Y10S438/938

    摘要： A method of fabricating semiconductor devices is provided. A plurality of gate structures is formed over a substrate. A source region and a drain region are formed in the substrate and adjacent to sidewalls of each gate structure. A self-aligned salicide block (SAB) layer is formed over the substrate to cover the gate structures and the exposed surface of the substrate. An anneal process is performed. The SAB layer creates a tension stress during the anneal process so that the substrate under the gate structures is subjected to the tension stress. A portion of the SAB layer is removed to expose a portion of the gate structures and a portion of the surface of the substrate. A salicide process is performed.

    摘要翻译： 提供一种制造半导体器件的方法。 在衬底上形成多个栅极结构。 源极区域和漏极区域形成在衬底中并且邻近每个栅极结构的侧壁。 在衬底上形成自对准的自对准硅化物块（SAB）层以覆盖栅极结构和衬底的暴露表面。 进行退火处理。 SAB层在退火过程中产生拉伸应力，使得栅极结构下的基板受到张力应力。 去除SAB层的一部分以暴露栅极结构的一部分和衬底表面的一部分。 执行自杀化合物处理。

    METHOD OF FABRICATING SEMICONDUCTOR DEVICES AND METHOD OF ADJUSTING LATTICE DISTANCE IN DEVICE CHANNEL
    8.
    发明申请
    METHOD OF FABRICATING SEMICONDUCTOR DEVICES AND METHOD OF ADJUSTING LATTICE DISTANCE IN DEVICE CHANNEL 审中-公开
    制造半导体器件的方法和调节器件通道中的晶体距离的方法

    公开(公告)号：US20060228843A1

    公开(公告)日：2006-10-12

    申请号：US10907677

    申请日：2005-04-12

    申请人： Alex Liu ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

    发明人： Alex Liu ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

    IPC分类号： H01L21/8234 ,  H01L21/336

    CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845 ,  Y10S438/938

    摘要： A method of fabricating semiconductor devices is provided. A plurality of gate structures is formed over a substrate. A source region and a drain region are formed in the substrate and adjacent to sidewalls of each gate structure. A self-aligned salicide block (SAB) layer is formed over the substrate to cover the gate structures and the exposed surface of the substrate. An anneal process is performed. The SAB layer creates a tension stress during the anneal process so that the substrate under the gate structures is subjected to the tension stress. A portion of the SAB layer is removed to expose a portion of the gate structures and a portion of the surface of the substrate. A salicide process is performed.

    摘要翻译： 提供一种制造半导体器件的方法。 在衬底上形成多个栅极结构。 源极区域和漏极区域形成在衬底中并且邻近每个栅极结构的侧壁。 在衬底上形成自对准的自对准硅化物块（SAB）层以覆盖栅极结构和衬底的暴露表面。 进行退火处理。 SAB层在退火过程中产生拉伸应力，使得栅极结构下的基板受到张力应力。 去除SAB层的一部分以暴露栅极结构的一部分和衬底表面的一部分。 执行自杀化合物处理。

    Method of fabricating semiconductor devices and method of adjusting lattice distance in device channel
    9.
    发明授权
    Method of fabricating semiconductor devices and method of adjusting lattice distance in device channel 有权
    半导体器件制造方法及器件通道中晶格距离的调整方法

    公开(公告)号：US07462542B2

    公开(公告)日：2008-12-09

    申请号：US11936093

    申请日：2007-11-07

    申请人： Alex Liu ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

    发明人： Alex Liu ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845 ,  Y10S438/938

    摘要： A method of fabricating semiconductor devices is provided. A plurality of gate structures is formed over a substrate. A source region and a drain region are formed in the substrate and adjacent to sidewalls of each gate structure. A self-aligned salicide block (SAB) layer is formed over the substrate to cover the gate structures and the exposed surface of the substrate. An anneal process is performed. The SAB layer creates a tension stress during the anneal process so that the substrate under the gate structures is subjected to the tension stress. A portion of the SAB layer is removed to expose a portion of the gate structures and a portion of the surface of the substrate. A salicide process is performed.

    摘要翻译： 提供一种制造半导体器件的方法。 在衬底上形成多个栅极结构。 源极区域和漏极区域形成在衬底中并且邻近每个栅极结构的侧壁。 在衬底上形成自对准的自对准硅化物块（SAB）层以覆盖栅极结构和衬底的暴露表面。 进行退火处理。 SAB层在退火过程中产生拉伸应力，使得栅极结构下的基板受到张力应力。 去除SAB层的一部分以暴露栅极结构的一部分和衬底表面的一部分。 执行自杀化合物处理。