公开(公告)号：US20060104145A1

公开(公告)日：2006-05-18

申请号：US10990237

申请日：2004-11-16

申请人： Alexandre Andreev ,  Igor Vikhliantsev ,  Ivan Pavisic

发明人： Alexandre Andreev ,  Igor Vikhliantsev ,  Ivan Pavisic

IPC分类号： G11C8/00

CPC分类号： G06F17/5045

摘要： A method of tiling a customer memory design to configurable memory blocks within a standardized memory matrix. A customer memory capacity and a customer memory width is determined for the customer memory design, and a standardized memory capacity and a standardized memory width is determined for the configurable memory blocks. The customer memory capacity and the customer memory width are selectively transformed by inverse factors based at least in part on a comparison of the customer memory capacity and the standardized memory capacity. Case independent blocks are formed within the configurable memory blocks, where the case independent blocks include gate structures formed in a standardized array in a substrate in which the customer memory design is to be implemented. Case dependent blocks are formed within the configurable memory blocks, where the case dependent blocks are electrically conductive routing layers that selectively connect the case independent blocks according to the transformation of the customer memory design.

摘要翻译： 将客户存储器设计平铺到标准化存储器矩阵内的可配置存储器块的方法。 为客户存储器设计确定客户存储器容量和客户存储器宽度，并且为可配置存储器块确定标准化存储容量和标准化存储器宽度。 至少部分地基于客户存储器容量与标准化存储器容量的比较，客户存储器容量和客户存储器宽度被反向因素选择性地变换。 在可配置的存储器块内形成与箱体无关的块，其中与壳体无关的块包括形成在衬底中的标准化阵列中的栅极结构，其中将实现客户存储器设计。 在可配置的存储器块内部形成与情况相关的块，其中与盒相关的块是根据客户存储器设计的变换选择性地连接不依赖于盒的块的导电路由层。

公开(公告)号：US07207026B2

公开(公告)日：2007-04-17

申请号：US10990237

申请日：2004-11-16

申请人： Alexandre Andreev ,  Igor Vikhliantsev ,  Ivan Pavisic

发明人： Alexandre Andreev ,  Igor Vikhliantsev ,  Ivan Pavisic

IPC分类号： G06F17/50 ,  H03K19/00

CPC分类号： G06F17/5045

摘要： A method of tiling a customer memory design to configurable memory blocks within a standardized memory matrix. A customer memory capacity and a customer memory width is determined for the customer memory design, and a standardized memory capacity and a standardized memory width is determined for the configurable memory blocks. The customer memory capacity and the customer memory width are selectively transformed by inverse factors based at least in part on a comparison of the customer memory capacity and the standardized memory capacity. Case independent blocks are formed within the configurable memory blocks, where the case independent blocks include gate structures formed in a standardized array in a substrate in which the customer memory design is to be implemented. Case dependent blocks are formed within the configurable memory blocks, where the case dependent blocks are electrically conductive routing layers that selectively connect the case independent blocks according to the transformation of the customer memory design.

摘要翻译： 将客户存储器设计平铺到标准化存储器矩阵内的可配置存储器块的方法。 为客户存储器设计确定客户存储器容量和客户存储器宽度，并且为可配置存储器块确定标准化存储容量和标准化存储器宽度。 至少部分地基于客户存储器容量与标准化存储器容量的比较，客户存储器容量和客户存储器宽度被反向因素选择性地变换。 在可配置的存储器块内形成与箱体无关的块，其中与壳体无关的块包括形成在衬底中的标准化阵列中的栅极结构，其中将实现客户存储器设计。 在可配置的存储器块内部形成与情况相关的块，其中与盒相关的块是根据客户存储器设计的变换选择性地连接不依赖于盒的块的导电路由层。

公开(公告)号：US20090243657A1

公开(公告)日：2009-10-01

申请号：US12058881

申请日：2008-03-31

申请人： Alexander Andreev ,  Ivan Pavisic ,  Igor Vikhliantsev

发明人： Alexander Andreev ,  Ivan Pavisic ,  Igor Vikhliantsev

IPC分类号： H03K19/096 ,  H01S4/00 ,  H03L7/00

CPC分类号： G11C19/00 ,  G06F9/3869 ,  Y10T29/49002

摘要： Methods and apparatus are provided for a fast unbalanced pipeline architecture. A disclosed pipeline buffer comprises a plurality of memory registers connected in series, each of the plurality of memory registers, such as flip-flops, having an enable input and a clock input; and a controlling memory register having an output that drives the enable inputs of the plurality of memory registers, whereby a predefined binary value on an input of the controlling memory register shifts values of the plurality of memory registers on a next clock cycle. A plurality of the disclosed pipeline buffets can be configured in a multiple stage configuration. At least one of the plurality of memory registers can comprise a locking memory register that synchronizes the pipeline buffer. The pipeline buffer can optionally include a delay gate to delay a clock signal and an inverter to invert the delayed clock signal. The clock signal can be delayed by the delay gate such that an output of the pipeline buffer is applied to a next stage of a pipeline buffer at a correct time.

摘要翻译： 为快速不平衡管道架构提供了方法和装置。 公开的流水线缓冲器包括串联连接的多个存储器寄存器，多个存储器寄存器中的每一个，诸如触发器，具有使能输入和时钟输入; 以及控制存储器寄存器，其具有驱动多个存储器寄存器的使能输入的输出，由此控制存储器寄存器的输入上的预定二进制值在下一个时钟周期上移位多个存储器寄存器的值。 多个公开的管道自助餐可以被配置为多级配置。 多个存储寄存器中的至少一个可以包括同步流水线缓冲器的锁存储寄存器。 流水线缓冲器可以可选地包括延迟门以延迟时钟信号和反相器以反转延迟的时钟信号。 时钟信号可以由延迟门延迟，使得流水线缓冲器的输出在正确的时间被施加到流水线缓冲器的下一级。

公开(公告)号：US07667494B2

公开(公告)日：2010-02-23

申请号：US12058881

申请日：2008-03-31

申请人： Alexander Andreev ,  Ivan Pavisic ,  Igor Vikhliantsev

发明人： Alexander Andreev ,  Ivan Pavisic ,  Igor Vikhliantsev

IPC分类号： G11C19/00 ,  H03K19/173

CPC分类号： G11C19/00 ,  G06F9/3869 ,  Y10T29/49002

摘要： Methods and apparatus are provided for a fast unbalanced pipeline architecture. A disclosed pipeline buffer comprises a plurality of memory registers connected in series, each of the plurality of memory registers, such as flip-flops, having an enable input and a clock input; and a controlling memory register having an output that drives the enable inputs of the plurality of memory registers, whereby a predefined binary value on an input of the controlling memory register shifts values of the plurality of memory registers on a next clock cycle. A plurality of the disclosed pipeline buffets can be configured in a multiple stage configuration. At least one of the plurality of memory registers can comprise a locking memory register that synchronizes the pipeline buffer. The pipeline buffer can optionally include a delay gate to delay a clock signal and an inverter to invert the delayed clock signal. The clock signal can be delayed by the delay gate such that an output of the pipeline buffer is applied to a next stage of a pipeline buffer at a correct time.

摘要翻译： 为快速不平衡管道架构提供了方法和装置。 公开的流水线缓冲器包括串联连接的多个存储器寄存器，多个存储器寄存器中的每一个，诸如触发器，具有使能输入和时钟输入; 以及控制存储器寄存器，其具有驱动多个存储器寄存器的使能输入的输出，由此控制存储器寄存器的输入上的预定二进制值在下一个时钟周期上移位多个存储器寄存器的值。 多个公开的管道自助餐可以被配置为多级配置。 多个存储寄存器中的至少一个可以包括同步流水线缓冲器的锁存储寄存器。 流水线缓冲器可以可选地包括延迟门以延迟时钟信号和反相器以反转延迟的时钟信号。 时钟信号可以由延迟门延迟，使得流水线缓冲器的输出在正确的时间被施加到流水线缓冲器的下一级。

公开(公告)号：US07093228B2

公开(公告)日：2006-08-15

申请号：US10327304

申请日：2002-12-20

申请人： Alexandre Andreev ,  Ivan Pavisic ,  Lav Ivanovic

发明人： Alexandre Andreev ,  Ivan Pavisic ,  Lav Ivanovic

IPC分类号： G06F17/50

CPC分类号： G03F1/36 ,  G03F7/70441

摘要： A method and system for performing optical proximity correction (OPC) on an integrated circuit (IC) chip design is disclosed. The system and method of the present invention includes dividing the IC chip into a plurality of local task regions, identifying congruent local task regions, classifying congruent local task regions into corresponding groups, and performing OPC for each group of congruent local task regions.By identifying and grouping congruent local task regions in the IC chip, according to the method and system disclosed herein, only one OPC procedure (e.g., evaluation and correction) needs to be performed per group of congruent local task regions. The amount of data to be evaluated and the number of corrections performed is greatly reduced because OPC is not performed on repetitive portions of the IC chip design, thereby resulting in significant savings in computing resources and time.

摘要翻译： 公开了一种在集成电路（IC）芯片设计上执行光学邻近校正（OPC）的方法和系统。 本发明的系统和方法包括将IC芯片划分为多个本地任务区域，识别同一个本地任务区域，将等同的本地任务区域分类为相应的组，并为每组全局本地任务区域执行OPC。 通过根据本文所公开的方法和系统识别和分组IC芯片中的一致的本地任务区域，需要在每一组一致的本地任务区域中执行一个OPC过程（例如，评估和校正）。 由于不对IC芯片设计的重复部分执行OPC，所以要评估的数据量和校正次数大大降低，从而大大节省了计算资源和时间。

公开(公告)号：US20110258587A1

公开(公告)日：2011-10-20

申请号：US13173855

申请日：2011-06-30

申请人： Andrey Nikitin ,  Ranko Scepanovic ,  Igor Kucherenko ,  William Lau ,  Cheng-Gang Kong ,  Hui-Yin Seto ,  Andrej Zolotykh ,  Ivan Pavisic ,  Sandeep Bhutani ,  Aiguo Lu ,  Ilya Lyalin

发明人： Andrey Nikitin ,  Ranko Scepanovic ,  Igor Kucherenko ,  William Lau ,  Cheng-Gang Kong ,  Hui-Yin Seto ,  Andrej Zolotykh ,  Ivan Pavisic ,  Sandeep Bhutani ,  Aiguo Lu ,  Ilya Lyalin

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/84

摘要： A system and method are provided for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist having components and connection paths among the components; identifying a first connection path in the initial netlist that comprises path fragments for which there are no equivalent path fragments in a second connection path in the initial netlist; generating a skew-corrected netlist wherein the second connection path is re-routed to have path fragments equivalent to the path fragments of the first connection path; and outputting the skew-corrected netlist.

摘要翻译： 根据各种实施例，提供了一种用于减少信号延迟偏差的系统和方法。 本公开的一个说明性实施例涉及一种方法。 根据一个说明性实施例，该方法包括：接收在组件之间具有组件和连接路径的初始网表; 识别所述初始网表中的第一连接路径，其包括在所述初始网表中的第二连接路径中不存在等效路径片段的路径片段; 生成偏差校正网表，其中所述第二连接路径被重新路由以具有等同于所述第一连接路径的路径片段的路径片段; 并输出偏差校正的网表。

公开(公告)号：US20090187873A1

公开(公告)日：2009-07-23

申请号：US12015925

申请日：2008-01-17

申请人： Andrey Nikitin ,  Ranko Scepanovic ,  Igor Kucherenko ,  William Lau ,  Cheng-Gang Kong ,  Hui-Yin Seto ,  Andrej Zolotykh ,  Ivan Pavisic ,  Sandeep Bhutani ,  Aiguo Lu ,  Ilya Lyalin

发明人： Andrey Nikitin ,  Ranko Scepanovic ,  Igor Kucherenko ,  William Lau ,  Cheng-Gang Kong ,  Hui-Yin Seto ,  Andrej Zolotykh ,  Ivan Pavisic ,  Sandeep Bhutani ,  Aiguo Lu ,  Ilya Lyalin

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/84

摘要： A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method further includes identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding skew-influencing features in a second connection path in the initial netlist. The method also includes generating a skew-corrected netlist wherein the second connection path includes one or more added skew-influencing features corresponding to those of the first connection path. The method further includes outputting the skew-corrected netlist.

摘要翻译： 根据各种实施例，公开了一种用于减小信号延迟偏差的系统。 本公开的一个说明性实施例涉及一种方法。 根据一个说明性实施例，该方法包括接收包括组件之间的组件和连接路径的初始网表。 该方法还包括识别在初始网表中的第一连接路径中的一个或多个偏斜影响特征，其在初始网表中的第二连接路径中缺少对应的偏斜影响特征。 该方法还包括生成偏差校正网表，其中第二连接路径包括与第一连接路径的相应的一个或多个相加的偏斜影响特征。 该方法还包括输出经偏斜校正的网表。

公开(公告)号：US07546505B2

公开(公告)日：2009-06-09

申请号：US11557513

申请日：2006-11-08

申请人： Sergey Gribok ,  Alexander Andreev ,  Ivan Pavisic

发明人： Sergey Gribok ,  Alexander Andreev ,  Ivan Pavisic

IPC分类号： G01R31/28 ,  G11C29/00

CPC分类号： G11C29/16 ,  G11C29/34 ,  G11C2029/0401 ,  G11C2029/1204 ,  G11C2029/2602

摘要： A built in self test circuit in a memory matrix. Memory cells within the matrix are disposed into columns. The circuit has only one memory test controller, adapted to initiate commands and receive results. Transport controllers are paired with the columns of memory cells. The controllers receive commands from the memory test controller, test memory cells within the column, receive test results, and provide the results to the memory test controller. The transport controllers operate in three modes. A production testing mode tests the memory cells in different columns, accumulating the results for a given column with the controller associated with the column. A production testing mode retrieves the results from the controllers. A diagnostic testing mode tests memory cells within one column, while retrieving results for the column.

摘要翻译： 内存自检电路在内存矩阵中。 矩阵内的存储单元被排列成列。 该电路只有一个内存测试控制器，适用于启动命令并接收结果。 传输控制器与存储单元的列配对。 控制器从存储器测试控制器接收命令，测试列内的测试存储单元，接收测试结果，并将结果提供给存储器测试控制器。 运输控制器以三种模式运行。 生产测试模式测试不同列中的存储单元，使用与列相关联的控制器累积给定列的结果。 生产测试模式从控制器检索结果。 诊断测试模式测试一列内的存储单元，同时检索列的结果。

公开(公告)号：US07243324B2

公开(公告)日：2007-07-10

申请号：US11041489

申请日：2005-01-24

申请人： Aiguo Lu ,  Ivan Pavisic ,  Nikola Radovanovic

发明人： Aiguo Lu ,  Ivan Pavisic ,  Nikola Radovanovic

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/505 ,  G06F2217/62

摘要： A method of buffer insertion for a tree network in an integrated circuit design includes steps of: (a) receiving as input an integrated circuit design including a tree network; (b) selecting a buffer type available to the integrated circuit design from a cell library that results in a minimum total delay for a predetermined wire length; (c) identifying each candidate leaf node in the tree network that has a required pin-specific target delay; (d) inserting a buffer between each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network and each leaf node that is not a candidate leaf node; (e) creating a buffer sub-tree in the tree network from an upstream internal node for each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network; re-parenting each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network to a new buffer in the buffer sub-tree; and (g) generating as output a revised integrated circuit design that includes the buffer sub-tree.

摘要翻译： 一种用于集成电路设计中的树形网络的缓冲器插入方法包括以下步骤：（a）接收作为输入的包括树形网络的集成电路设计; （b）从单元库选择可用于集成电路设计的缓冲器类型，其导致预定导线长度的最小总延迟; （c）识别树网络中具有所需针特定目标延迟的候选叶节点; （d）在由候选叶节点到树网络的根节点的路径穿过的每个内部节点之间插入缓冲器，并且不是候选叶节点的每个叶节点; （e）从由候选叶节点到树网络的根节点的路径遍历的每个内部节点的上游内部节点在树形网络中创建缓冲器子树; 将通过从候选叶节点到树树网络的根节点的路径遍历的每个内部节点重新编入缓冲器子树中的新缓冲器; 和（g）产生包括缓冲器子树的经修订的集成电路设计的输出。

公开(公告)号：US06901571B1

公开(公告)日：2005-05-31

申请号：US09010396

申请日：1998-01-21

申请人： Dusan Petranovic ,  Ranko Scepanovic ,  Ivan Pavisic

发明人： Dusan Petranovic ,  Ranko Scepanovic ,  Ivan Pavisic

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A method for optimal placement of cells on a surface of an integrated circuit, comprising the steps of comparing a placement of cells to predetermined cost criteria and moving cells to alternate locations on the surface if necessary to satisfy the cost criteria. The cost criteria include a timing criterion based upon interconnect delay, where interconnect delay is modeled as a RC tree expressed as a function of pin-to-pin distance. The method accounts for driver to sink interconnect delay at the placement level, a novel aspect resulting from use of the RC tree model, which maximally utilizes available net information to produce an optimal timing estimate. Preferred versions utilize a RC tree interconnect delay model that is consistent with timing models used at design levels above placement, such as synthesis, and below placement, such as routing. Additionally, preferred versions can utilize either a constructive placement or iterative improvement placement method.

摘要翻译： 一种用于在集成电路的表面上最佳地放置单元的方法，包括以下步骤：如果需要满足成本标准，将单元的布局与预定成本标准进行比较并将单元移动到表面上的替代位置。 成本标准包括基于互连延迟的定时标准，其中互连延迟被建模为作为针对针距离的函数的RC树。 该方法考虑了驱动程序以在布局级别中接收互连延迟，这是由使用RC树模型产生的新颖的方面，其最大限度地利用可用的网络信息来产生最佳的时序估计。 首选版本使用RC树互连延迟模型，其与在布局之上的设计级别（例如合成）以及在布局之下（例如路由）使用的定时模型一致。 另外，优选版本可以利用建设性位置或迭代改进放置方法。