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公开(公告)号：US20090281969A1
公开(公告)日：2009-11-12
申请号：US12117851
申请日：2008-05-09
IPC分类号： G06F15/18
CPC分类号： G06F17/505
摘要： An arbitrary function may be represented as an optimized decision tree. The decision tree may be calculated, pruned, and factored to create a highly optimized set of equations, much of which may be represented by simple circuits and little, if any, complex processing. A circuit design system may automate the decision tree generation, optimization, and circuit generation for an arbitrary function. The circuits may be used for processing digital signals, such as soft decoding and other processes, among other uses.
摘要翻译： 任意函数可以表示为优化决策树。 决策树可以被计算，修剪和因子分解以创建高度优化的方程组，其中大部分可以由简单的电路和很少的（如果有的话）复杂的处理来表示。 电路设计系统可以自动执行任意功能的决策树生成，优化和电路生成。 这些电路可以用于处理数字信号，诸如软解码和其他处理以及其它用途。
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公开(公告)号：US20080178057A1
公开(公告)日：2008-07-24
申请号：US11626400
申请日：2007-01-24
IPC分类号： H03M13/00
CPC分类号： H03M13/1145
摘要： An improvement to an arithmetic unit of a low-density parity-check decoder, where the arithmetic unit has a pipelined architecture of modules. A first module calculates a difference between absolute values of md_R and md_g_in, and passes the result to a first Gallager module. The first Gallager module converts this value from a p0/p1 representation to a 2*p0−1 representation, and passes the result to a second module. The second module selectively adjusts the result of the previous module based on the sign values of md_g_in and md_R, and passes one of its outputs to a third module (the other two outputs, loc_item_out and hard_out, are not a part of the pipeline). The third module calculates a new md_g value by adding the result of the second module and loc_item_in, and passes this result to a fourth module. The fourth module separates a sign and an absolute value of the new md_g, and passes the result to a second Gallager module. The second Gallager module converts the result from the 2*p0−1 representation to the p0/p1 representation and the final value leaves the unit as md_g_out. In these calculations, md_R=a check node value from the previous iteration, md_g=an edge value (md_g_in—from the previous iteration, md_g_out—for the next iteration), p0=probability that a value is zero, p1=probability that a value is one, loc_item_in/loc_item_out=intermediate values used for the md_g_out calculation, and hard_out=a bit value estimation for the current iteration of the pipelined arithmetic unit.
摘要翻译： 对低密度奇偶校验解码器的算术单元的改进，其中算术单元具有模块的流水线架构。 第一模块计算md_R和md_g_in的绝对值之间的差值，并将结果传递给第一个Gallager模块。 第一个Gallager模块将该值从p0 / p1表示转换为2 * p0-1表示，并将结果传递给第二个模块。 第二个模块根据md_g_in和md_R的符号值有选择地调整前一个模块的结果，并将其一个输出传递给第三个模块（另外两个输出loc_item_out和hard_out不是流水线的一部分）。 第三个模块通过添加第二个模块的结果和loc_item_in来计算一个新的md_g值，并将该结果传递给第四个模块。 第四个模块分离新的md_g的符号和绝对值，并将结果传递给第二个Gallager模块。 第二个Gallager模块将2 * p0-1表示的结果转换为p0 / p1表示，最终值将单位设为md_g_out。 在这些计算中，md_R =来自前一次迭代的校验节点值，md_g =边缘值（md_g_in - 来自上一次迭代，md_g_out-用于下一次迭代），p0 =值为零的概率，p1 = 值为1，loc_item_in / loc_item_out =用于md_g_out计算的中间值，hard_out =流水线运算单元当前迭代的位值估计。
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公开(公告)号：US07028274B1
公开(公告)日：2006-04-11
申请号：US11054460
申请日：2005-02-09
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method for transforming a customer's memory design into an RRAM memory design. A port mapping table is created that lists the ports of the customer memories, and an instance types table is created that lists the customer memories. For each customer memory that is listed in the instance types table, any virtual buffer nets are removed, and any virtual buffers are removed. Any loose nets so created are reconnected to an RRAM cell in the RRAM memory design. The customer memory instance are then removed. A constraints file is updated from customer memory port designations to RRAM port designations. Automated test logic is inserted into the RRAM memory design, layout on the RRAM memory design is performed, and timing constraints on the RRAM memory design are satisfied. A modified version of the RRAM memory design is returned to the customer for verification. The modified version is made using the port mapping table. Each RRAM matrix is replaced with the customer memories it replaced, the removed virtual buffer nets and virtual buffers are left out, and other parts of the RRAM memory design are left unchanged.
摘要翻译： 将客户的存储器设计转换为RRAM存储器设计的方法。 创建一个端口映射表，其中列出了客户端口的存储器，并创建了一个列出客户内存的实例类型表。 对于实例类型表中列出的每个客户内存，将删除任何虚拟缓冲区网络，并删除任何虚拟缓冲区。 任何如此创建的松散网络都将重新连接到RRAM内存设计中的RRAM单元。 然后删除客户内存实例。 约束文件从客户内存端口名称更新为RRAM端口名称。 将自动测试逻辑插入到RRAM存储器设计中，执行RRAM存储器设计的布局，并满足RRAM存储器设计的时序约束。 将修改版本的RRAM存储器设计返回给客户进行验证。 修改版本使用端口映射表进行。 每个RRAM矩阵被替换的客户存储器替代，删除的虚拟缓冲器网络和虚拟缓冲器被省略，并且RRAM存储器设计的其他部分保持不变。
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公开(公告)号：US07739575B2
公开(公告)日：2010-06-15
申请号：US11626400
申请日：2007-01-24
IPC分类号： H03M13/00
CPC分类号： H03M13/1145
摘要： An improvement to an arithmetic unit of a low-density parity-check decoder, where the arithmetic unit has a pipelined architecture of modules. A first module calculates a difference between absolute values of md_R and md_g_in, and passes the result to a first Gallager module. The first Gallager module converts this value from a p0/p1 representation to a 2*p0−1 representation, and passes the result to a second module. The second module selectively adjusts the result of the previous module based on the sign values of md_g_in and md_R, and passes one of its outputs to a third module (the other two outputs, loc_item_out and hard_out, are not a part of the pipeline). The third module calculates a new md_g value by adding the result of the second module and loc_item_in, and passes this result to a fourth module. The fourth module separates a sign and an absolute value of the new md_g, and passes the result to a second Gallager module. The second Gallager module converts the result from the 2*p0−1 representation to the p0/p1 representation and the final value leaves the unit as md_g_out. In these calculations, md_R=a check node value from the previous iteration, md_g=an edge value (md_g_in—from the previous iteration, md_g_out—for the next iteration), p0=probability that a value is zero, p1=probability that a value is one, loc_item_in/loc_item_out=intermediate values used for the md_g_out calculation, and hard_out=a bit value estimation for the current iteration of the pipelined arithmetic unit.
摘要翻译： 对低密度奇偶校验解码器的算术单元的改进，其中算术单元具有模块的流水线架构。 第一模块计算md_R和md_g_in的绝对值之间的差值，并将结果传递给第一个Gallager模块。 第一个Gallager模块将该值从p0 / p1表示转换为2 * p0-1表示，并将结果传递给第二个模块。 第二个模块根据md_g_in和md_R的符号值有选择地调整前一个模块的结果，并将其一个输出传递给第三个模块（另外两个输出loc_item_out和hard_out不是流水线的一部分）。 第三个模块通过添加第二个模块的结果和loc_item_in来计算一个新的md_g值，并将该结果传递给第四个模块。 第四个模块分离新的md_g的符号和绝对值，并将结果传递给第二个Gallager模块。 第二个Gallager模块将2 * p0-1表示的结果转换为p0 / p1表示，最终值将单位设为md_g_out。 在这些计算中，md_R =来自前一次迭代的校验节点值，md_g =边缘值（md_g_in - 来自上一次迭代，md_g_out-用于下一次迭代），p0 =值为零的概率，p1 = 值为1，loc_item_in / loc_item_out =用于md_g_out计算的中间值，hard_out =流水线运算单元当前迭代的位值估计。
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5.发明申请公开(公告)号：US20090309770A1
公开(公告)日：2009-12-17
申请号：US12138920
申请日：2008-06-13
申请人： Alexander Andreev , Sergey Gribok , Oleg Izyumin , Ranko Scepanovic , Igor Vikhliantsev , Vojislav Vukovic
发明人： Alexander Andreev , Sergey Gribok , Oleg Izyumin , Ranko Scepanovic , Igor Vikhliantsev , Vojislav Vukovic
IPC分类号： H03M7/00
CPC分类号： H03M13/296 , H03M13/2725 , H03M13/6508 , H03M13/6513 , H03M13/6519 , H03M13/6525 , H03M13/6544 , H03M13/6569
摘要： Methods and apparatus are provided for programmable decoding of a plurality of code types. A method is provided for decoding data encoded using one of a plurality of code types, where each of the code types correspond to a communication standard. The code type associated with the data is identified and the data is allocated to a plurality of programmable parallel decoders. The programmable parallel decoders can be reconfigured to decode data encoded using each of the plurality of code types. A method is also provided for interleaving data among M parallel decoders using a communications network. An interleaver table is employed, wherein each entry in the interleaver table identifies one of the M parallel decoders as a target decoder and a target address of a communications network for interleaved data. Data is interleaved by writing the data to the target address of the communications network. The communications network can comprise, for example, a cross-bar switch and/or one or more first-in-first-out buffers.
摘要翻译： 提供了用于多种代码类型的可编程解码的方法和装置。 提供了一种用于解码使用多种代码类型之一编码的数据的方法，其中每种代码类型对应于通信标准。 识别与数据相关联的代码类型，并将数据分配给多个可编程并行解码器。 可重新配置可编程并行解码器以对使用多种代码类型中的每一种编码的数据进行解码。 还提供了一种用于使用通信网络在M个并行解码器之间交织数据的方法。 使用交织器表，其中交织器表中的每个条目将M个并行解码器中的一个识别为目标解码器，并将交织数据的通信网络的目标地址标识。 通过将数据写入到通信网络的目标地址来交织数据。 通信网络可以包括例如交叉开关和/或一个或多个先入先出缓冲器。
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6.发明授权Methods and apparatus for programmable decoding of a plurality of code types 有权用于多种代码类型的可编程解码的方法和装置公开(公告)号：US08035537B2
公开(公告)日：2011-10-11
申请号：US12138920
申请日：2008-06-13
申请人： Alexander Andreev , Sergey Gribok , Oleg Izyumin , Ranko Scepanovic , Igor Vikhliantsev , Vojislav Vukovic
发明人： Alexander Andreev , Sergey Gribok , Oleg Izyumin , Ranko Scepanovic , Igor Vikhliantsev , Vojislav Vukovic
IPC分类号： H03M7/00
CPC分类号： H03M13/296 , H03M13/2725 , H03M13/6508 , H03M13/6513 , H03M13/6519 , H03M13/6525 , H03M13/6544 , H03M13/6569
摘要： Methods and apparatus are provided for programmable decoding of a plurality of code types. A method is provided for decoding data encoded using one of a plurality of code types, where each of the code types correspond to a communication standard. The code type associated with the data is identified and the data is allocated to a plurality of programmable parallel decoders. The programmable parallel decoders can be reconfigured to decode data encoded using each of the plurality of code types. A method is also provided for interleaving data among M parallel decoders using a communications network. An interleaver table is employed, wherein each entry in the interleaver table identifies one of the M parallel decoders as a target decoder and a target address of a communications network for interleaved data. Data is interleaved by writing the data to the target address of the communications network. The communications network can comprise, for example, a cross-bar switch and/or one or more first-in-first-out buffers.
摘要翻译： 提供了用于多种代码类型的可编程解码的方法和装置。 提供了一种用于解码使用多种代码类型之一编码的数据的方法，其中每种代码类型对应于通信标准。 识别与数据相关联的代码类型，并将数据分配给多个可编程并行解码器。 可重新配置可编程并行解码器以对使用多种代码类型中的每一种编码的数据进行解码。 还提供了一种用于使用通信网络在M个并行解码器之间交织数据的方法。 使用交织器表，其中交织器表中的每个条目将M个并行解码器中的一个识别为目标解码器，并将交织数据的通信网络的目标地址标识。 通过将数据写入到通信网络的目标地址来交织数据。 通信网络可以包括例如交叉开关和/或一个或多个先入先出缓冲器。
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公开(公告)号：US20060236194A1
公开(公告)日：2006-10-19
申请号：US11455903
申请日：2006-06-19
IPC分类号： H03M13/00
CPC分类号： H03M13/6505 , H03M13/27 , H03M13/2957 , H03M13/6566
摘要： A decoder for access data stored in n memories comprises a function matrix containing addresses of the memory locations at unique coordinates. A decomposer sorts addresses from coordinate locations of first and second m×n matrices, such that each row contains no more than one address from the same memory. Positional apparatus stores entries in third and fourth m×n matrices identifying coordinates of addresses in the function matrix such that each entry in the third matrix is at coordinates that matches corresponding coordinates in the first matrix, and each entry in the fourth matrix is at coordinates that matches corresponding coordinates in the second matrix. The decoder is responsive to entries in the matrices for accessing data in parallel from the memories.
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公开(公告)号：US20050053182A1
公开(公告)日：2005-03-10
申请号：US10656195
申请日：2003-09-04
CPC分类号： H04L7/02 , H03M9/00 , Y10T436/143333
摘要： A frequency reduction or phase shifting circuit has an input receiving an input data stream having an input frequency and a representation of desired output frequency. A splitter splits the input data stream into a plurality of split signals each at a frequency of the desired output frequency. A plurality of catchers identify valid bits of each respective split signal. A shifter shifts valid bits identified by at least some of the catchers by a predetermined number which establishes a de-serialization level for frequency reduction or phase shifting. An output provide an output data stream at the desired output frequency.
摘要翻译： 频率降低或移相电路具有接收具有输入频率和所需输出频率的表示的输入数据流的输入。 分流器将输入数据流分成多个分离信号，每个信号以期望的输出频率的频率分段。 多个捕获器识别每个相应的分离信号的有效位。 移位器将由至少一些捕获器识别的有效位移位预定数量，其建立用于频率降低或相移的解串级。 输出提供所需输出频率的输出数据流。
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公开(公告)号：US06587990B1
公开(公告)日：2003-07-01
申请号：US09678201
申请日：2000-10-01
IPC分类号： G06F1750
CPC分类号： G06F17/505
摘要： The present invention is a method and apparatus for optimizing the design of a combinational circuit. The method includes constructing a circuit sheaf for the combinational circuit and then performing vector optimization with domination. In the preferred embodiment, a complete BDD B is determined and, from that, a list of F-sets is computed. If the combinational circuit includes cells other than NOT, AND and XOR cells, the circuit is first transformed such that it only has those types of cells.
摘要翻译： 本发明是一种优化组合电路设计的方法和装置。 该方法包括为组合电路构建电路束，然后进行矢量优化。 在优选实施例中，确定完整的BDD B，并且从中计算出F组的列表。 如果组合电路包括除NOT，AND和XOR单元以外的单元，则首先对电路进行转换，使其仅具有这些类型的单元。
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公开(公告)号：US08735857B2
公开(公告)日：2014-05-27
申请号：US13271679
申请日：2011-10-12
CPC分类号： H03K19/17728 , H03K19/17796
摘要： A via-configurable circuit block may contain chains of p-type and n-type transistors that may or may not be interconnected by means of configurable vias. Configurable vias may also be used to connect various transistor terminals to a ground line, a power line and/or to various terminals that may provide connections outside of the circuit block.
摘要翻译： 通孔可配置电路块可以包含可以或可以不通过可配置通孔互连的p型和n型晶体管链。 可配置的通孔也可用于将各种晶体管端子连接到接地线，电力线和/或可提供电路块外部的连接的各种端子。
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