公开(公告)号：US06593200B2

公开(公告)日：2003-07-15

申请号：US09989649

申请日：2001-11-20

申请人： Alexander Kalnitsky ,  Dmitri A. Choutov ,  Geoffrey C. Stutzin ,  Robert F. Scheer

发明人： Alexander Kalnitsky ,  Dmitri A. Choutov ,  Geoffrey C. Stutzin ,  Robert F. Scheer

IPC分类号： H01L21331

CPC分类号： H01L28/10 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a semiconductor device with an inductor and/or high speed interconnect. The method comprises forming an epitaxial layer over the substrate, forming an opening through the epitaxial layer to expose an underlying region of the substrate, forming a first dielectric material within the opening of the epitaxial layer, planarizing the first dielectric layer, forming a second dielectric material layer over the first dielectric material layer, and then forming a metallized inductor over the second dielectric material layer above the opening of the epitaxial layer. In this case, since the inductor and the high speed interconnect do not overlie the conductive epitaxial layer, the degradation in the Q-factor of the inductor, loss characteristics of the high speed interconnect, and ‘cross-talk’ between conductors are substantially reduced. The resulting semiconductor device is also disclosed.

摘要翻译： 一种形成具有电感器和/或高速互连的半导体器件的方法。 该方法包括在衬底上形成外延层，形成穿过外延层的开口以暴露衬底的下部区域，在外延层的开口内形成第一电介质材料，使第一电介质层平坦化，形成第二电介质 材料层，然后在外延层的开口上方的第二介电材料层上形成金属化电感器。 在这种情况下，由于电感器和高速互连不会覆盖在导电外延层上，电感器的Q因子的劣化，高速互连的损耗特性和导体之间的“串扰”大大降低 还公开了所得到的半导体器件。

公开(公告)号：US06303413B1

公开(公告)日：2001-10-16

申请号：US09564178

申请日：2000-05-03

申请人： Alexander Kalnitsky ,  Dmitri A. Choutov ,  Robert F. Scheer ,  Fanling H. Yang ,  Thomas W. Dobson ,  Tadanori Yamaguchi ,  Geoffrey C. Stutzin ,  Ken Liao

发明人： Alexander Kalnitsky ,  Dmitri A. Choutov ,  Robert F. Scheer ,  Fanling H. Yang ,  Thomas W. Dobson ,  Tadanori Yamaguchi ,  Geoffrey C. Stutzin ,  Ken Liao

IPC分类号： H01L2100

CPC分类号： H01L21/76264 ,  H01L21/76275 ,  H01L21/76283 ,  H01L21/76286

摘要： A method of forming a shallow-deep trench isolation (SDTI) is provided that includes the steps of forming a pair of deep trenches through a silicon on insulator (SOI) layer without substantially disturbing an underlying buried oxide (BOX) layer. Once the deep trenches are formed, the trenches are filed with suitable electrical isolating materials, such as undoped poly-silicon or dielectric material, and etched back to obtain a substantially planarized top surface. Subsequently, an active nitride layer is deposited on the planarized top surface, and then a pair of shallow trenches are formed. The shallow trenches are formed using a low selectivity etch to uniformly etch a deep trench liner oxide, the SOI layer and the electrical isolating material which have interfaces at non-perpendicular angles with respect to the direction of the etching. Once the shallow and deep trenches are formed, subsequent processing including filling the shallow trench, annealing and chemical-mechanical polishing can be performed.

摘要翻译： 提供了形成浅深沟槽隔离（SDTI）的方法，其包括以下步骤：通过绝缘体上硅（SOI）层形成一对深沟槽，而不会基本上干扰下面的掩埋氧化物（BOX）层。 一旦形成了深沟槽，则沟槽用合适的电绝缘材料（例如未掺杂的多晶硅或电介质材料）放置并且被回蚀以获得基本平坦化的顶表面。 随后，在平坦化的顶表面上沉积活性氮化物层，然后形成一对浅沟槽。 使用低选择性蚀刻来形成浅沟槽以均匀蚀刻深沟槽衬垫氧化物，SOI层和电绝缘材料，其具有相对于蚀刻方向以非垂直角度的界面。 一旦形成浅沟槽和深沟槽，就可以执行包括填充浅沟槽，退火和化学机械抛光的后续处理。

公开(公告)号：US06479394B1

公开(公告)日：2002-11-12

申请号：US09564327

申请日：2000-05-03

申请人： Dmitri A. Choutov ,  Alexander Kalnitsky ,  Geoffrey C. Stutzin

发明人： Dmitri A. Choutov ,  Alexander Kalnitsky ,  Geoffrey C. Stutzin

IPC分类号： H01L21302

CPC分类号： H01L21/31111 ,  H01L21/3065 ,  H01L21/32137

摘要： A method of etching dissimilar materials having interfaces at non-perpendicular angles to the direction of the etch propagation that results in a low selectivity etch in order to achieve an improved planarized etched surface. The method includes the step of subjecting the dissimilar materials to a process gas mixture that includes a first gas that dominates the etching of a first material and a second gas that dominates the etching of a second material. The flow rates for the first and second materials are selected, along with other parameters of the plasma etch apparatus, to substantially equalize the etching rates for the two materials. This method is particularly useful to achieve a low-selective etching of materials having interfaces that are at a non-perpendicular angle with respect to the etch propagation.

摘要翻译： 蚀刻不同材料的方法，其具有与蚀刻传播方向成非垂直角的界面，导致低选择性蚀刻以实现改进的平坦化蚀刻表面。 该方法包括将不同材料经受处理气体混合物的步骤，该工艺气体混合物包括支配第一材料的蚀刻的第一气体和支配第二材料蚀刻的第二气体。 选择第一和第二材料的流速以及等离子体蚀刻装置的其它参数，以使两种材料的蚀刻速率基本相等。 该方法对于实现具有相对于蚀刻传播处于非垂直角的界面的材料的低选择性蚀刻特别有用。