利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

66 条记录 (耗时 0.021 秒)

    Low temperature sacrificial oxide formation
    1.
    发明授权
    Low temperature sacrificial oxide formation 有权
    低温牺牲氧化物形成

    公开(公告)号：US06309983B1

    公开(公告)日：2001-10-30

    申请号：US09324926

    申请日：1999-06-03

    申请人： Alexander Michaeli ,  Stephan Kudelka

    发明人： Alexander Michaeli ,  Stephan Kudelka

    IPC分类号： H01L2131

    CPC分类号： H01L21/02238 ,  H01L21/02258 ,  H01L21/31675

    摘要： A method for depositing a sacrificial oxide for fabricating a semiconductor device includes preparing p-doped silicon regions on a semiconductor wafer for depositing a sacrificial oxide on the p-doped silicon regions. The method also includes the step of placing the wafer in an electrochemical cell such that a solution including electrolytes interacts with the p-doped silicon regions to form a sacrificial oxide on the p-doped silicon regions when a potential difference is provided between the wafer and the solution. Processing the wafer using the sacrificial oxide layer is also included.

    摘要翻译： 用于沉积用于制造半导体器件的牺牲氧化物的方法包括在半导体晶片上制备用于在p掺杂硅区域上沉积牺牲氧化物的p掺杂硅区域。 该方法还包括以下步骤：将晶片放置在电化学电池中，使得包含电解质的溶液与p掺杂的硅区相互作用以在p掺杂的硅区上形成牺牲氧化物，当晶片和 解决方案。 还包括使用牺牲氧化物层处理晶片。

    Selective etching to increase trench surface area
    2.
    发明授权
    Selective etching to increase trench surface area 有权
    选择性蚀刻以增加沟槽表面积

    公开(公告)号：US07157328B2

    公开(公告)日：2007-01-02

    申请号：US11047312

    申请日：2005-01-31

    申请人： Helmut Horst Tews ,  Stephan Kudelka ,  Kenneth T. Settlemyer

    发明人： Helmut Horst Tews ,  Stephan Kudelka ,  Kenneth T. Settlemyer

    IPC分类号： H01L21/8242

    CPC分类号： H01L21/30604 ,  H01L29/66181

    摘要： The surface area of the walls of a trench formed in a substrate is increased. A barrier layer is formed on the walls of the trench such that the barrier layer is thinner near the corners of the trench and is thicker between the corners of the trench. A dopant is introduced into the substrate through the barrier layer to form higher doped regions in the substrate near the corners of the trench and lesser doped regions between the corners of the trench. The barrier layer is removed, and the walls of the trench are etched in a manner that etches the lesser doped regions of the substrate at a higher rate than the higher doped regions of the substrate to widen and lengthen the trench and to form rounded corners at the intersections of the walls of the trench.

    摘要翻译： 在衬底中形成的沟槽的壁的表面积增加。 阻挡层形成在沟槽的壁上，使得阻挡层在沟槽的角部附近更薄，并且在沟槽的角部之间更厚。 通过势垒层将掺杂剂引入到衬底中，以在衬底附近的沟槽的角部附近形成更高的掺杂区域，并且在沟槽的角部之间形成较小的掺杂区域。 去除阻挡层，并且以如下方式蚀刻沟槽的壁，该方式是以比衬底的较高掺杂区域更高的速率蚀刻衬底的较小掺杂区域，以加宽和延长沟槽并且形成圆角 沟渠墙壁的交叉点。

    Selective etching to increase trench surface area
    3.
    发明申请
    Selective etching to increase trench surface area 有权
    选择性蚀刻以增加沟槽表面积

    公开(公告)号：US20060172486A1

    公开(公告)日：2006-08-03

    申请号：US11047312

    申请日：2005-01-31

    申请人： Helmut Tews ,  Stephan Kudelka ,  Kenneth Settlemyer

    发明人： Helmut Tews ,  Stephan Kudelka ,  Kenneth Settlemyer

    IPC分类号： H01L21/8242 ,  H01L29/94

    CPC分类号： H01L21/30604 ,  H01L29/66181

    摘要： The surface area of the walls of a trench formed in a substrate is increased. A barrier layer is formed on the walls of the trench such that the barrier layer is thinner near the corners of the trench and is thicker between the corners of the trench. A dopant is introduced into the substrate through the barrier layer to form higher doped regions in the substrate near the corners of the trench and lesser doped regions between the corners of the trench. The barrier layer is removed, and the walls of the trench are etched in a manner that etches the lesser doped regions of the substrate at a higher rate than the higher doped regions of the substrate to widen and lengthen the trench and to form rounded corners at the intersections of the walls of the trench.

    摘要翻译： 在衬底中形成的沟槽的壁的表面积增加。 阻挡层形成在沟槽的壁上，使得阻挡层在沟槽的角部附近更薄，并且在沟槽的角部之间更厚。 通过势垒层将掺杂剂引入到衬底中，以在衬底附近的沟槽的角部附近形成更高的掺杂区域，并且在沟槽的角部之间形成较小的掺杂区域。 去除阻挡层，并且以如下方式蚀刻沟槽的壁，该方式是以比衬底的较高掺杂区域更高的速率蚀刻衬底的较小掺杂区域，以加宽和延长沟槽并且形成圆角 沟渠墙壁的交叉点。

    Method for fabricating trench capacitor with insulation collar electrically connected to substrate through buried contact, in particular, for a semiconductor memory cell
    6.
    发明申请
    Method for fabricating trench capacitor with insulation collar electrically connected to substrate through buried contact, in particular, for a semiconductor memory cell 失效
    用于制造具有绝缘环的沟槽电容器的方法，所述绝缘套环通过埋入触点电连接到衬底，特别是用于半导体存储器单元

    公开(公告)号：US20050026384A1

    公开(公告)日：2005-02-03

    申请号：US10901406

    申请日：2004-07-27

    申请人： Stephan Kudelka ,  Martin Popp ,  Harald Seidl ,  Annette Sanger

    发明人： Stephan Kudelka ,  Martin Popp ,  Harald Seidl ,  Annette Sanger

    IPC分类号： H01L21/20 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/1087 ,  H01L27/10829 ,  H01L29/66181

    摘要： Fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected thereto on one side through a buried contact, in particular, for a semiconductor memory cell with a planar selection transistor in the substrate and connected through the buried contact, includes providing a trench using an opening in a hard mask, providing a capacitor dielectric in lower and central trench regions, the collar in central and upper trench regions, and a conductive filling at least as far as the insulation collar topside, completely filling the trench with a filling material, carrying out STI trench fabrication process, removing the filling material and sinking the filling to below the collar topside, forming an insulation region on one side above the collar; uncovering a connection region on a different side above the collar, and forming the buried contact by depositing and etching back a metallic filling.

    摘要翻译： 在衬底中制造具有绝缘套环的沟槽电容器，其在一侧通过埋入触点电连接，特别地，用于具有衬底中的平面选择晶体管并通过埋入触点连接的半导体存储器单元包括提供 在硬掩模中使用开口的沟槽，在下部和中部沟槽区域中提供电容器电介质，在中央和上部沟槽区域中的套环，以及至少与绝缘套环顶部一样的导电填充物，完全用一个 填充材料，执行STI沟槽制造工艺，去除填充材料并将填充物下沉到轴环顶部以下，在轴环上方的一侧上形成绝缘区域; 露出套环上方不同侧的连接区域，并通过沉积和蚀刻金属填充物来形成掩埋触点。

    High aspect ratio PBL SiN barrier formation
    7.
    发明授权
    High aspect ratio PBL SiN barrier formation 有权
    高纵横比PBL SiN阻挡层形成

    公开(公告)号：US06677197B2

    公开(公告)日：2004-01-13

    申请号：US10032040

    申请日：2001-12-31

    申请人： Stephan Kudelka ,  Helmut Horst Tews

    发明人： Stephan Kudelka ,  Helmut Horst Tews

    IPC分类号： H01L218242

    CPC分类号： H01L27/1087 ,  H01L29/66181

    摘要： In a process for preparing a DT DRAM for sub 100 nm groundrules that normally require the formation of a collar after the bottle formation, the improvement of providing a collar first scheme by forming a high aspect ration PBL SiN barrier, comprising: a) providing a semiconductor structure after SiN node deposition and DT polysilicon fill; b) depositing a poly buffered LOCOS (PBL) Si liner; c) subjecting the PBL liner to oxidation to form a pad oxide and depositing a SiN barrier layer; d) depositing a silicon mask liner; e) subjecting the DT to high directional ion implantation (I/I) using a p-dopant; f) employing a selective wet etch of unimplanted Si with an etch stop on SiN; g) subjecting the product of step f) to a SiN wet etch with an etch stop on the pad oxide; h) affecting a Si liner etch with a stop on the pad oxide; i) oxidizing the PBL Si liner and affecting a barrier SiN strip; j) providing a DT polysilicon fill and performing a poly chemical mechanical polishing.

    摘要翻译： 在制备通常需要在瓶形成后形成套环的亚100nm研磨剂制备DT DRAM的方法中，通过形成高面积比PBL SiN阻挡层来改进提供轴环第一方案，该方法包括：a） 在SiN结点沉积和DT多晶硅填充之后的半导体结构; b）沉积多层缓冲LOCOS（PBL）Si衬垫; c）使PBL衬里氧化形成衬垫氧化物并沉积SiN阻挡层; d）沉积硅掩模 衬垫; e）使用p-掺杂剂对DT进行高定向离子注入（I / I）; f）使用SiN上的蚀刻停止对未被注入的Si的选择性湿蚀刻; g）使步骤f）的产物 在衬垫氧化物上具有蚀刻停止层的SiN湿蚀刻; h）影响衬垫氧化物上的停止的Si衬层蚀刻; i）氧化PBL Si衬垫并影响势垒SiN条; j）提供DT多晶硅填充物 进行多化学机械抛光。

    Negative ion implant mask formation for self-aligned, sublithographic resolution patterning for single-sided vertical device formation
    9.
    发明授权
    Negative ion implant mask formation for self-aligned, sublithographic resolution patterning for single-sided vertical device formation 失效
    用于单面垂直器件形成的自对准，亚光刻分辨率图案的负离子注入掩模形成

    公开(公告)号：US06498061B2

    公开(公告)日：2002-12-24

    申请号：US09730674

    申请日：2000-12-06

    申请人： Rama Divakaruni ,  Stephan Kudelka ,  Helmut Tews ,  Irene McStay ,  Kil-Ho Lee ,  Uwe Schroeder

    发明人： Rama Divakaruni ,  Stephan Kudelka ,  Helmut Tews ,  Irene McStay ,  Kil-Ho Lee ,  Uwe Schroeder

    IPC分类号： H01L218242

    CPC分类号： H01L27/10867

    摘要： A process for fabricating a single-sided semiconductor deep trench structure filled with polysilicon trench fill material includes the following steps. Form a thin film, silicon nitride, barrier layer over the trench fill material. Deposit a thin film of an amorphous silicon masking layer over the barrier layer. Perform an angled implant into portions of the amorphous silicon masking layer which are not in the shadow of the deep trench. Strip the undoped portions of the amorphous silicon masking layer from the deep trench. Then strip the newly exposed portions of barrier layer exposing a part of the trench fill polysilicon surface and leaving the doped, remainder of the amorphous silicon masking layer exposed. Counterdope the exposed part of the trench fill material. Oxidize exposed portions of the polysilicon trench fill material, and then strip the remainder of the masking layer.

    摘要翻译： 用于制造填充有多晶硅沟槽填充材料的单面半导体深沟槽结构的工艺包括以下步骤。 在沟槽填充材料上形成薄膜，氮化硅，阻挡层。 在阻挡层上沉积非晶硅掩模层的薄膜。 对非深度沟槽阴影的非晶硅掩模层的部分进行成角度的注入。 从深沟槽剥离非晶硅掩模层的未掺杂部分。 然后剥离暴露部分沟槽填充多晶硅表面的势垒层的新暴露部分，并且使非晶硅掩模层的掺杂剩余部分露出。 反映出暴露部分的沟槽填充材料。 氧化多晶硅沟槽填充材料的暴露部分，然后剥离掩模层的其余部分。

    Temperature controlled degassification of deionized water for megasonic cleaning of semiconductor wafers
    10.
    发明授权
    Temperature controlled degassification of deionized water for megasonic cleaning of semiconductor wafers 有权
    用于超声波清洗半导体晶片的去离子水温度控制脱气

    公开(公告)号：US06167891A

    公开(公告)日：2001-01-02

    申请号：US09318156

    申请日：1999-05-25

    申请人： Stephan Kudelka ,  David Rath

    发明人： Stephan Kudelka ,  David Rath

    IPC分类号： B08B312

    CPC分类号： H01L21/67057 ,  B08B3/12 ,  B08B2203/002

    摘要： A system is provided to prepare deionized water having a 100% saturated concentration of a gas, e.g., nitrogen, at a hot temperature, e.g., 50-85° C., and an attendant pressure, e.g., atmospheric pressure, to clean a semiconductor wafer, e.g., of silicon. The gas concentration of deionized water having a predetermined concentration of the gas at a cold temperature, e.g., 15-30° C., is adjusted in a degassifier chamber having a vacuum pump and a pressure sensor, to provide an under-saturated concentration of the gas at the cold temperature corresponding to the saturated concentration thereof at the hot temperature and attendant pressure. The adjusted gas concentration water is then heated in a heating vessel having a heater and a temperature sensor, to the hot temperature to form a hot bath having such saturated gas concentration to clean the wafer, e.g., in a cleaning tank under megasonic vibrations. A controller is connected to the pump, pressure sensor, heater and temperature sensor to control the chamber pressure and vessel temperature.

    摘要翻译： 提供一种系统来制备具有100％饱和浓度的气体（例如氮气）的去离子水，其在例如50-85℃的热温度和伴随的压力（例如大气压）下清洁半导体 晶片，例如硅。 在具有真空泵和压力传感器的脱气室中调节在例如15-30℃的冷温度下具有预定浓度的气体的去离子水的气体浓度，以提供不饱和的浓度 在温度较低的温度下，与其饱和浓度对应的气体和伴随的压力。 然后将经调节的气体浓度的水在具有加热器和温度传感器的加热容器中加热到热的温度，以形成具有饱和气体浓度的热浴，以清洁晶片，例如在超声波振动下的清洗槽中。 控制器连接到泵，压力传感器，加热器和温度传感器，以控制腔室的压力和容器温度。