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    Negative ion implant mask formation for self-aligned, sublithographic resolution patterning for single-sided vertical device formation
    2.
    发明授权
    Negative ion implant mask formation for self-aligned, sublithographic resolution patterning for single-sided vertical device formation 失效
    用于单面垂直器件形成的自对准，亚光刻分辨率图案的负离子注入掩模形成

    公开(公告)号：US06498061B2

    公开(公告)日：2002-12-24

    申请号：US09730674

    申请日：2000-12-06

    申请人： Rama Divakaruni ,  Stephan Kudelka ,  Helmut Tews ,  Irene McStay ,  Kil-Ho Lee ,  Uwe Schroeder

    发明人： Rama Divakaruni ,  Stephan Kudelka ,  Helmut Tews ,  Irene McStay ,  Kil-Ho Lee ,  Uwe Schroeder

    IPC分类号： H01L218242

    CPC分类号： H01L27/10867

    摘要： A process for fabricating a single-sided semiconductor deep trench structure filled with polysilicon trench fill material includes the following steps. Form a thin film, silicon nitride, barrier layer over the trench fill material. Deposit a thin film of an amorphous silicon masking layer over the barrier layer. Perform an angled implant into portions of the amorphous silicon masking layer which are not in the shadow of the deep trench. Strip the undoped portions of the amorphous silicon masking layer from the deep trench. Then strip the newly exposed portions of barrier layer exposing a part of the trench fill polysilicon surface and leaving the doped, remainder of the amorphous silicon masking layer exposed. Counterdope the exposed part of the trench fill material. Oxidize exposed portions of the polysilicon trench fill material, and then strip the remainder of the masking layer.

    摘要翻译： 用于制造填充有多晶硅沟槽填充材料的单面半导体深沟槽结构的工艺包括以下步骤。 在沟槽填充材料上形成薄膜，氮化硅，阻挡层。 在阻挡层上沉积非晶硅掩模层的薄膜。 对非深度沟槽阴影的非晶硅掩模层的部分进行成角度的注入。 从深沟槽剥离非晶硅掩模层的未掺杂部分。 然后剥离暴露部分沟槽填充多晶硅表面的势垒层的新暴露部分，并且使非晶硅掩模层的掺杂剩余部分露出。 反映出暴露部分的沟槽填充材料。 氧化多晶硅沟槽填充材料的暴露部分，然后剥离掩模层的其余部分。

    Selective etching to increase trench surface area
    4.
    发明申请
    Selective etching to increase trench surface area 有权
    选择性蚀刻以增加沟槽表面积

    公开(公告)号：US20060172486A1

    公开(公告)日：2006-08-03

    申请号：US11047312

    申请日：2005-01-31

    申请人： Helmut Tews ,  Stephan Kudelka ,  Kenneth Settlemyer

    发明人： Helmut Tews ,  Stephan Kudelka ,  Kenneth Settlemyer

    IPC分类号： H01L21/8242 ,  H01L29/94

    CPC分类号： H01L21/30604 ,  H01L29/66181

    摘要： The surface area of the walls of a trench formed in a substrate is increased. A barrier layer is formed on the walls of the trench such that the barrier layer is thinner near the corners of the trench and is thicker between the corners of the trench. A dopant is introduced into the substrate through the barrier layer to form higher doped regions in the substrate near the corners of the trench and lesser doped regions between the corners of the trench. The barrier layer is removed, and the walls of the trench are etched in a manner that etches the lesser doped regions of the substrate at a higher rate than the higher doped regions of the substrate to widen and lengthen the trench and to form rounded corners at the intersections of the walls of the trench.

    摘要翻译： 在衬底中形成的沟槽的壁的表面积增加。 阻挡层形成在沟槽的壁上，使得阻挡层在沟槽的角部附近更薄，并且在沟槽的角部之间更厚。 通过势垒层将掺杂剂引入到衬底中，以在衬底附近的沟槽的角部附近形成更高的掺杂区域，并且在沟槽的角部之间形成较小的掺杂区域。 去除阻挡层，并且以如下方式蚀刻沟槽的壁，该方式是以比衬底的较高掺杂区域更高的速率蚀刻衬底的较小掺杂区域，以加宽和延长沟槽并且形成圆角 沟渠墙壁的交叉点。

    Structure and method for improved isolation in trench storage cells
    6.
    发明授权
    Structure and method for improved isolation in trench storage cells 失效
    用于改善沟槽存储单元隔离的结构和方法

    公开(公告)号：US06437401B1

    公开(公告)日：2002-08-20

    申请号：US09824957

    申请日：2001-04-03

    申请人： Jack A. Mandelman ,  Stephan Kudelka ,  Andreas Knorr ,  Stephen Rahn ,  Helmut Tews ,  Michael Wise

    发明人： Jack A. Mandelman ,  Stephan Kudelka ,  Andreas Knorr ,  Stephen Rahn ,  Helmut Tews ,  Michael Wise

    IPC分类号： H01L2976

    CPC分类号： H01L27/1087 ,  H01L27/10861 ,  H01L27/10864 ,  H01L29/945

    摘要： A trench capacitor structure for improved charge retention and method of manufacturing thereof are provided. A trench is formed in a p-type conductivity semiconductor substrate. An isolation collar is located in an upper portion of the trench. The substrate adjacent the upper portion of the trench contains a first n+ type conductivity region and a second n+ type conductivity region. These regions each abut a wall of the trench and are separated vertically by a portion of the p-type conductivity semiconductor substrate. A void which encircles the perimeter of the trench is formed into the wall of the trench and is located in the substrate between the first and second n+ type conductivity regions.

    摘要翻译： 提供了用于改善电荷保留的沟槽电容器结构及其制造方法。 在p型导电性半导体衬底中形成沟槽。 隔离套环位于沟槽的上部。 与沟槽上部相邻的衬底包含第一n +型导电区​​和第二n +型导电区​​。 这些区域各自邻接沟槽的壁并且被p型导电性半导体衬底的一部分垂直分开。 围绕沟槽的周边的空隙形成沟槽的壁，并且位于第一和第二n +型导电区​​域之间的衬底中。

    Trench capacitor with buried strap
    7.
    发明授权
    Trench capacitor with buried strap 有权
    带埋地带的沟槽电容器

    公开(公告)号：US07157329B2

    公开(公告)日：2007-01-02

    申请号：US11053508

    申请日：2005-02-08

    申请人： Helmut Tews ,  Jochen Beintner ,  Stephan Kudelka

    发明人： Helmut Tews ,  Jochen Beintner ,  Stephan Kudelka

    IPC分类号： H01L21/8234

    CPC分类号： H01L27/10867 ,  H01L27/10864

    摘要： A trench capacitor with improved strap is disclosed. The strap is located above the top surface of the capacitor. The top surface of the trench capacitor, which is formed by the top surfaces of the collar and storage plate, is planar. By locating the strap on a planar surface, the divot present in conventional strap processes is avoided. This results in improved strap reliability and device performance.

    摘要翻译： 公开了一种具有改进带的沟槽电容器。 带子位于电容器顶表面之上。 沟槽电容器的由表圈和存储板的顶表面形成的顶表面是平面的。 通过将带固定在平坦的表面上，避免了传统带状过程中存在的裂纹。 这样可以提高表带的可靠性和设备性能。

    Trench capacitor with buried strap
    8.
    发明申请
    Trench capacitor with buried strap 有权
    带埋地带的沟槽电容器

    公开(公告)号：US20050158961A1

    公开(公告)日：2005-07-21

    申请号：US11053508

    申请日：2005-02-08

    申请人： Helmut Tews ,  Jochen Beintner ,  Stephan Kudelka

    发明人： Helmut Tews ,  Jochen Beintner ,  Stephan Kudelka

    IPC分类号： H01L21/20 ,  H01L21/8242 ,  H01L27/108 ,  H01L33/00

    CPC分类号： H01L27/10867 ,  H01L27/10864

    摘要： A trench capacitor with improved strap is disclosed. The strap is located above the top surface of the capacitor. The top surface of the trench capacitor, which is formed by the top surfaces of the collar and storage plate, is planar. By locating the strap on a planar surface, the divot present in conventional strap processes is avoided. This results in improved strap reliability and device performance.

    摘要翻译： 公开了一种具有改进带的沟槽电容器。 带子位于电容器顶表面之上。 沟槽电容器的由表圈和存储板的顶表面形成的顶表面是平面的。 通过将带固定在平坦的表面上，避免了传统带状过程中存在的裂纹。 这样可以提高表带的可靠性和设备性能。

    Trench capacitor with buried strap
    9.
    发明授权
    Trench capacitor with buried strap 失效
    带埋地带的沟槽电容器

    公开(公告)号：US06853025B2

    公开(公告)日：2005-02-08

    申请号：US10248801

    申请日：2003-02-20

    申请人： Helmut Tews ,  Jochen Beintner ,  Stephan Kudelka

    发明人： Helmut Tews ,  Jochen Beintner ,  Stephan Kudelka

    IPC分类号： H01L21/20 ,  H01L21/8242 ,  H01L27/108 ,  H01L33/00

    CPC分类号： H01L27/10867 ,  H01L27/10864

    摘要： A trench capacitor with improved strap is disclosed. The strap is located above the top surface of the capacitor. The top surface of the trench capacitor which is formed by the top surfaces of the collar and storage plate, is planar. By locating the strap on a planar surface, the divot present in conventional strap processes is avoided. This results in improved strap reliability and device performance.

    摘要翻译： 公开了一种具有改进带的沟槽电容器。 带子位于电容器顶表面之上。 由套环和储存板的顶表面形成的沟槽电容器的顶表面是平面的。 通过将带固定在平坦的表面上，避免了传统带状过程中存在的裂纹。 这样可以提高表带的可靠性和设备性能。

    Method of forming low-leakage on-chip capacitor
    10.
    发明授权
    Method of forming low-leakage on-chip capacitor 失效
    形成低漏电片上电容器的方法

    公开(公告)号：US06451662B1

    公开(公告)日：2002-09-17

    申请号：US09970635

    申请日：2001-10-04

    申请人： Michael Chudzik ,  Oleg Gluschenkov ,  Raj Jammy ,  Uwe Schroeder ,  Helmut Tews

    发明人： Michael Chudzik ,  Oleg Gluschenkov ,  Raj Jammy ,  Uwe Schroeder ,  Helmut Tews

    IPC分类号： H01L2120

    CPC分类号： H01L27/10861 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02326 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/31662 ,  H01L21/32105

    摘要： An improved capacitor is formed by a process where an improved node dielectric layer is formed with an improved dielectric constant by performing an Free Radical Enhanced Rapid Thermal Oxidation (FRE RTO) step during formation of the node dielectric layer. Use of an FRE RTO step instead of the conventional furnace oxidation step produces a cleaner oxide with a higher dielectric constant and higher capacitance. Other specific embodiments of the invention include improved node dielectric layer by one or more additional nitridation steps, done by either Remote Plasma Nitridation (RPN), Rapid Thermal Nitridation (RTN), Decoupled Plasma Nitridation (DPN) or other nitridation method; selective oxidation; use of a metal layer rather than a SiN layer as the dielectric base; and selective oxidation of the metal layer.

    摘要翻译： 通过在形成节点介质层期间通过执行自由基增强快速热氧化（FRE RTO）步骤而改进的介电常数形成改进的节点电介质层的工艺形成改进的电容器。 使用FRE RTO步骤代替常规炉氧化步骤产生具有更高介电常数和较高电容的清洁氧化物。 本发明的其它具体实施方案包括通过远程等离子体氮化（RPN），快速热氮化（RTN），去耦等离子体氮化（DPN）或其它氮化方法进行的一个或多个另外的氮化步骤改进的节点电介质层; 选择性氧化; 使用金属层而不是SiN层作为电介质基底; 和金属层的选择性氧化。