摘要:
A novel circuit is coupled to a memory device sense amplifier and a memory device output pin for driving the output pin with data. The circuit includes a first inverter (18) and a second inverter (100) coupled to the first inverter. Transfer gates (30, 104) are coupled across the input and output leads of the first and second inverters, respectively. During a first mode of operation, the first and second transfer gates are closed and the second inverter is three-stated so that the input and output leads of the first and second inverters are held at a voltage between VCC and ground. When it is desired to drive the memory device output pin with data, the first and second transfer gates open, and the second inverter leaves the three-state mode and goes into a low output impedance mode. Because the input and output leads of the first and second inverters are held at a voltage between VCC and ground when the transfer gates are closed, when the transfer gates open, the delay between the time the transfer gates open and the time valid output data appears on the output lead of the second inverter is minimized. The second inverter comprises large transistors and can therefore provide a large output current. However, because the second inverter is three-stated when the second transfer gate is closed, the circuit draws minimal power when the first and second transfer gates are closed.
摘要:
A method, system, and apparatus exist which couple a first group of non-redundant memory columns to a non-redundant input-output circuit and couple a second group of redundant memory columns to a redundant input-output circuit. A fewer amount of memory columns exist in the second group of redundant memory columns than in the first of non-redundant memory columns. A first fuse indicates whether one or more memory columns are defective in a group of non-redundant memory columns coupled to the non-redundant input output circuit. Also, a second fuse couples to a first circuit. The first circuit identifies which sub-input circuit is coupled to the one or more defective memory columns.
摘要:
Improving statistical yield of a system-on-a-chip. The system-on-a-chip includes several memory systems. Each memory system includes a large number of memories. The memories are tested to identify any faulty memories. One or more margins of the faulty memories are then varied and the memories are then tested again.
摘要:
A Static Random Access Memory (SRAM) cell having a source-biasing mechanism for leakage reduction. In standby mode, the cell's wordline is deselected and a source-biasing potential is provided to the cell. In read mode, the wordline is selected and responsive thereto, the source-biasing potential provided to the cell is deactivated. Upon completion of reading, the source-biasing potential is re-activated.
摘要:
A self-timed write control memory device minimizes the memory cycle time for the cells of the array. The self-timed write control memory device preferably comprises an X-decoder, a word-line driver, a memory cell array, control logic, pre-charge circuits, sense amplifiers, a reference decoder, and a reference word-line driver. The memory device preferably further includes a first reference cell, a second reference cell or logic, a first reference column, a second reference column and a reference sense amplifier. The first reference cell is preferably used for detection of read cycle completion and the second reference cell or logic is used for detection of write cycle completion. The output of the first reference cell and second reference cell are preferably coupled to inputs of a unique reference sense amplifier. The sense amplifier includes special circuitry that uses either the output of the first reference cell or the second reference cell to generate the self-timed clock and there by minimizes the memory cycle time. The second reference cell may be any one of a conventional memory cell or write reference logic.
摘要:
A new design methodology which utilizes a module-based architecture is used to implement customized VLSI designs. In accordance with this invention, the module-based architecture comprises a number of Matrix Transistor Logic (MTL) modules. Each MTL module has a control input buffer section, an output stage section, and a matrix array section. The matrix array section implements logic functions using Pass Transistor Logic technology. Three variables, each of which place a different constraint on the MTL modules, are used in an automated design procedure to implement the MTL modules.
摘要:
An embodiment of this invention provides an integrated circuit (IC) having a configurable peripheral port which includes an input/output pin, a multiplexer coupled to the input/output pin, volatile configuration bits to control the multiplexer, and non-volatile configuration bits to control the multiplexer and override the volatile configuration bits. One embodiment of an IC also includes a peripheral port as above and functional units, such as programmable array logic (PAL) and erasable programmable read only memory (EPROM), coupled to the multiplexer. In another embodiment, a non-volatile configuration bit from a functional unit configures an input/output pin when the configuration bit is not needed by the functional unit.
摘要:
A circuit constructed in accordance with my invention includes a microprocessor for generating addresses on an address bus, a plurality of memory devices, and a decoder for decoding the address on the address bus and generating select signals in response thereto. Of importance, the memory devices are also coupled to the address bus. A memory enable circuit is provided for enabling the memory devices before the decoder generates the select signals. Thus, the time required by the decoder to decode address signals does not add to the delay between the time an address is asserted by the microprocessor and the time one of the memory devices responds by providing data. In one embodiment, the memory enable circuit is incorporated into the bit line decoder of the memory devices. Thus, if one of the bit lines of the plurality of memory devices is selected to provide data, the memory device is enabled. Since the word line decoder is generally slower than the bit line decoder, inclusion of the memory enable circuit into the bit line decoder will not slow the memory devices. Also in one embodiment, the bit line decoder is programmable so that the memory devices can be mapped into different blocks of addresses within the microprocessor address space.
摘要:
A source-biasing mechanism for leakage reduction in SRAM. In standby mode, wordlines are deselected and a source-biasing potential is provided to SRAM cells. In read mode, a selected wordline deactivates the source-biasing potential provided to the selected row of SRAM cells, whereas the remaining SRAM cells on the selected bitline column continue to be source-biased.
摘要:
Methods and apparatuses in which a ROM memory array has virtual-grounded source lines programmed in layer physically higher than the diffusion layer. The ROM memory array may include a diffusion layer, one or more virtual-grounded source lines, and one or more bit lines. At least one of the virtual-grounded source lines is programmed with a layer physically higher than the diffusion layer.