公开(公告)号：US20120313180A1

公开(公告)日：2012-12-13

申请号：US13569730

申请日：2012-08-08

申请人： Allan T. Mitchell ,  Mark A. Eskew ,  Keith Jarreau

发明人： Allan T. Mitchell ,  Mark A. Eskew ,  Keith Jarreau

IPC分类号： H01L21/8239 ,  H01L27/088

CPC分类号： H01L27/11206 ,  G11C17/16 ,  H01L27/11226 ,  H01L29/4983 ,  H01L29/861

摘要： In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.

摘要翻译： 在本发明的实施例中，公开了一种非易失性反熔丝存储器单元。 存储单元由可编程的n沟道二极管连接晶体管组成。 晶体管的多晶硅栅极具有两部分。 一部分掺杂比第二部分更高。 晶体管还具有源的两部分，其中源的一部分被掺杂得比第二部分更高。 物理上更接近源极的栅极的部分比多晶硅栅极的其他部分更轻掺杂。 物理上更靠近聚硅氧烷栅极的轻掺杂部分的源的部分相对于源的另一部分被轻掺杂。 当晶体管被编程时，在重掺杂的聚硅氧烷栅极的部分中绝大多数情况下会发生破裂。

公开(公告)号：US08748235B2

公开(公告)日：2014-06-10

申请号：US13569730

申请日：2012-08-08

申请人： Allan T. Mitchell ,  Mark A. Eskew ,  Keith Jarreau

发明人： Allan T. Mitchell ,  Mark A. Eskew ,  Keith Jarreau

IPC分类号： H01L21/336

CPC分类号： H01L27/11206 ,  G11C17/16 ,  H01L27/11226 ,  H01L29/4983 ,  H01L29/861

摘要： In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.

摘要翻译： 在本发明的实施例中，公开了一种非易失性反熔丝存储器单元。 存储单元由可编程的n沟道二极管连接晶体管组成。 晶体管的多晶硅栅极具有两部分。 一部分掺杂比第二部分更高。 晶体管还具有源的两部分，其中源的一部分被掺杂得比第二部分更高。 物理上更接近源极的栅极的部分比多晶硅栅极的其他部分更轻掺杂。 物理上更靠近聚硅氧烷栅极的轻掺杂部分的源的部分相对于源的另一部分被轻掺杂。 当晶体管被编程时，在重掺杂的聚硅氧烷栅极的部分中绝大多数情况下会发生破裂。

公开(公告)号：US08258586B1

公开(公告)日：2012-09-04

申请号：US13045725

申请日：2011-03-11

申请人： Allan T. Mitchell ,  Mark A. Eskew ,  Keith Jarreau

发明人： Allan T. Mitchell ,  Mark A. Eskew ,  Keith Jarreau

IPC分类号： H01L27/115

CPC分类号： H01L27/11206 ,  G11C17/16 ,  H01L27/11226 ,  H01L29/4983 ,  H01L29/861

摘要： In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.

摘要翻译： 在本发明的实施例中，公开了一种非易失性反熔丝存储器单元。 存储单元由可编程的n沟道二极管连接晶体管组成。 晶体管的多晶硅栅极具有两部分。 一部分掺杂比第二部分更高。 晶体管还具有源的两部分，其中源的一部分被掺杂得比第二部分更高。 物理上更接近源极的栅极的部分比多晶硅栅极的其他部分更轻掺杂。 物理上更靠近聚硅氧烷栅极的轻掺杂部分的源的部分相对于源的另一部分被轻掺杂。 当晶体管被编程时，在重掺杂的聚硅氧烷栅极的部分中绝大多数情况下会发生破裂。

公开(公告)号：US20120228724A1

公开(公告)日：2012-09-13

申请号：US13045725

申请日：2011-03-11

申请人： Allan T. Mitchell ,  Mark A. Eskew ,  Keith Jarreau

发明人： Allan T. Mitchell ,  Mark A. Eskew ,  Keith Jarreau

IPC分类号： H01L23/525 ,  H01L21/8239

CPC分类号： H01L27/11206 ,  G11C17/16 ,  H01L27/11226 ,  H01L29/4983 ,  H01L29/861

摘要： In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.

摘要翻译： 在本发明的实施例中，公开了一种非易失性反熔丝存储器单元。 存储单元由可编程的n沟道二极管连接晶体管组成。 晶体管的多晶硅栅极具有两部分。 一部分掺杂比第二部分更高。 晶体管还具有源的两部分，其中源的一部分被掺杂得比第二部分更高。 物理上更接近源极的栅极的部分比多晶硅栅极的其他部分更轻掺杂。 物理上更靠近聚硅氧烷栅极的轻掺杂部分的源的部分相对于源的另一部分被轻掺杂。 当晶体管被编程时，在重掺杂的聚硅氧烷栅极的部分中绝大多数情况下会发生破裂。

公开(公告)号：US20110303959A1

公开(公告)日：2011-12-15

申请号：US12797971

申请日：2010-06-10

申请人： Allan T. Mitchell ,  Keith Jarreau

发明人： Allan T. Mitchell ,  Keith Jarreau

IPC分类号： H01L29/788 ,  H01L21/3205

CPC分类号： H01L23/552 ,  B81B7/0064 ,  H01L23/5225 ,  H01L27/11517 ,  H01L29/78633 ,  H01L2225/06537 ,  H01L2924/0002 ,  H01L2924/3025 ,  H01L2924/00

摘要： An integrated circuit with non-volatile memory cells shielded from ultraviolet light by a shielding structure compatible with chemical-mechanical processing. The disclosed shielding structure includes a roof structure with sides; along each side are spaced-apart contact posts, each with a width on the order of the wavelength of ultraviolet light to be shielded, and spaced apart by a distance that is also on the order of the wavelength of ultraviolet light to be shielded. The contact posts may be provided in multiple rows, and extending to a diffused region or to a polysilicon ring or both. The multiple rows may be aligned with one another or staggered relative to one another.

摘要翻译： 一种具有非易失性存储单元的集成电路，通过与化学机械处理兼容的屏蔽结构来屏蔽紫外线。 所公开的屏蔽结构包括具有侧面的屋顶结构; 沿着每一侧具有间隔开的接触柱，每个接触柱具有要被屏蔽的紫外线的波长的宽度，并隔开一定距离，该距离也在要被屏蔽的紫外线的波长的数量级上。 接触柱可以设置成多排，并且延伸到扩散区域或多晶硅环或两者。 多行可以彼此对准或相互交错排列。

公开(公告)号：US09406621B2

公开(公告)日：2016-08-02

申请号：US12797971

申请日：2010-06-10

申请人： Allan T. Mitchell ,  Keith Jarreau

发明人： Allan T. Mitchell ,  Keith Jarreau

IPC分类号： H01L23/552 ,  H01L23/522 ,  B81B7/00 ,  H01L29/786 ,  H01L27/115

CPC分类号： H01L23/552 ,  B81B7/0064 ,  H01L23/5225 ,  H01L27/11517 ,  H01L29/78633 ,  H01L2225/06537 ,  H01L2924/0002 ,  H01L2924/3025 ,  H01L2924/00

摘要： An integrated circuit with non-volatile memory cells shielded from ultraviolet light by a shielding structure compatible with chemical-mechanical processing. The disclosed shielding structure includes a roof structure with sides; along each side are spaced-apart contact posts, each with a width on the order of the wavelength of ultraviolet light to be shielded, and spaced apart by a distance that is also on the order of the wavelength of ultraviolet light to be shielded. The contact posts may be provided in multiple rows, and extending to a diffused region or to a polysilicon ring or both. The multiple rows may be aligned with one another or staggered relative to one another.

摘要翻译： 一种具有非易失性存储单元的集成电路，通过与化学机械处理兼容的屏蔽结构来屏蔽紫外线。 所公开的屏蔽结构包括具有侧面的屋顶结构; 沿着每一侧具有间隔开的接触柱，每个接触柱具有要被屏蔽的紫外线的波长的宽度，并隔开一定距离，该距离也在要被屏蔽的紫外线的波长的数量级上。 接触柱可以设置成多排，并且延伸到扩散区域或多晶硅环或两者。 多行可以彼此对准或相互交错排列。

公开(公告)号：US08716083B2

公开(公告)日：2014-05-06

申请号：US13359253

申请日：2012-01-26

申请人： Allan T. Mitchell ,  Imran Mahmood Khan ,  Michael A. Wu

发明人： Allan T. Mitchell ,  Imran Mahmood Khan ,  Michael A. Wu

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  H01L27/0805 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

摘要： An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes n-type and p-type doped portions serving as gate electrodes of n-channel and p-channel MOS transistors, respectively; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad. An opening at the surface of the analog floating-gate electrode, at the location at which n-type and p-type doped portions of the floating gate electrode abut, allow formation of silicide at that location, shorting the p-n junction.

摘要翻译： 集成电路中的模拟浮栅电极及其制造方法，其中捕获的电荷可以长时间存储。 模拟浮栅电极形成为多晶硅栅极电平，并且分别包括用作n沟道和p沟道MOS晶体管的栅电极的n型和p型掺杂部分。 金属对多晶硅储存电容器的板; 以及一块多至多层隧道电容器。 硅化物阻挡二氧化硅阻止在电极上形成硅化物包层，而集成电路中的其它多晶硅结构是硅化物包覆的。 在模拟浮栅电极的表面处，在浮栅电极的n型和p型掺杂部分邻接的位置处的开口允许在该位置形成硅化物，使p-n结短路。

公开(公告)号：US20130221418A1

公开(公告)日：2013-08-29

申请号：US13406704

申请日：2012-02-28

申请人： Allan T. Mitchell ,  Imran Mahmood Khan ,  Michael A. Wu

发明人： Allan T. Mitchell ,  Imran Mahmood Khan ,  Michael A. Wu

IPC分类号： H01L27/108 ,  H01L21/336

CPC分类号： H01L29/66825 ,  H01L21/2652 ,  H01L23/5223 ,  H01L27/11517 ,  H01L27/1156 ,  H01L28/40 ,  H01L28/60 ,  H01L29/105 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

摘要： An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, doped n-type throughout its length, and includes portions serving as gate electrodes of n-channel and p-channel MOS transistors; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. The p-channel MOS transistor includes a buried channel region, formed by way of ion implantation, disposed between its source and drain regions. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.

摘要翻译： 集成电路中的模拟浮栅电极及其制造方法，其中捕获的电荷可以长时间存储。 模拟浮栅电极形成为多晶硅栅极电平，在其整个长度上掺杂n型，并且包括用作n沟道和p沟道MOS晶体管的栅电极的部分; 金属对多晶硅储存电容器的板; 以及一块多至多层隧道电容器。 p沟道MOS晶体管包括通过离子注入形成的掩埋沟道区，设置在其源区和漏区之间。 硅化物阻挡二氧化硅阻止在电极上形成硅化物包层，而集成电路中的其它多晶硅结构是硅化物包覆的。

公开(公告)号：US20130043934A1

公开(公告)日：2013-02-21

申请号：US13199002

申请日：2011-08-17

申请人： David A. Heisley ,  Allan T. Mitchell

发明人： David A. Heisley ,  Allan T. Mitchell

IPC分类号： H03F3/45 ,  H03K17/693 ,  G05F3/02

CPC分类号： H03F3/45475 ,  H03F2203/45546 ,  H03F2203/45548

摘要： An analog floating gate circuit (10-3, 10-4) includes a first sense transistor (21, 3), a first storage capacitor (20, 5), and first (24, 4) and second (31A, 42) tunneling regions. Various portions of a first floating gate conductor (12, 2) form a floating gate of the first sense transistor, a floating first plate of the first storage capacitor (20, 5), a floating first plate of the first tunneling region, and a floating first plate of the second tunneling region, respectively. A second plate of the first storage capacitor is coupled to a first reference voltage (VREF, GND), and a second plate of the second tunneling region is coupled to a second reference voltage (VPROG/GND). Compensation circuitry (44-1, 44-2) is coupled to the first floating gate conductor, for compensating loss of trapped charge from the first floating gate conductor.

摘要翻译： 模拟浮动栅极电路（10-3,10-4）包括第一检测晶体管（21,3），第一存储电容器（20,5）和第一（24,4）和第二（31A，42）隧道 地区。 第一浮栅导体（12,2）的各部分形成第一检测晶体管的浮置栅极，第一存储电容器（20,5）的浮置第一板，第一隧穿区域的浮置第一板，以及第 分别是第二隧道区的浮动第一板。 第一存储电容器的第二板耦合到第一参考电压（VREF，GND），并且第二隧穿区域的第二板耦合到第二参考电压（VPROG / GND）。 补偿电路（44-1,44-2）耦合到第一浮栅导体，用于补偿来自第一浮栅导体的俘获电荷损失。

公开(公告)号：US20120244671A1

公开(公告)日：2012-09-27

申请号：US13359253

申请日：2012-01-26

申请人： Allan T. Mitchell ,  Imran Mahmood Khan ,  Michael A. Wu

发明人： Allan T. Mitchell ,  Imran Mahmood Khan ,  Michael A. Wu

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  H01L27/0805 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

摘要： An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes n-type and p-type doped portions serving as gate electrodes of n-channel and p-channel MOS transistors, respectively; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad. An opening at the surface of the analog floating-gate electrode, at the location at which n-type and p-type doped portions of the floating gate electrode abut, allow formation of silicide at that location, shorting the p-n junction.

摘要翻译： 集成电路中的模拟浮栅电极及其制造方法，其中捕获的电荷可以长时间存储。 模拟浮栅电极形成为多晶硅栅极电平，并且分别包括用作n沟道和p沟道MOS晶体管的栅电极的n型和p型掺杂部分。 金属对多晶硅储存电容器的板; 以及一块多至多层隧道电容器。 硅化物阻挡二氧化硅阻止在电极上形成硅化物包层，而集成电路中的其它多晶硅结构是硅化物包覆的。 在模拟浮栅电极的表面处，在浮栅电极的n型和p型掺杂部分邻接的位置处的开口允许在该位置形成硅化物，使p-n结短路。