公开(公告)号：US10482934B2

公开(公告)日：2019-11-19

申请号：US15878182

申请日：2018-01-23

申请人： Altera Corporation

发明人： Chee Hak Teh

IPC分类号： G11C7/22 ,  G06F13/16 ,  H03K19/177

摘要： Integrated circuits that include memory interface and controller circuitry for communicating with external memory are provided. The memory interface and controller circuitry may include a user logic interface, a memory controller, and a physical layer input-output interface. The user logic interface may be operated in a first clock domain. The memory controller may be operated in a second clock domain. The physical layer interface may be operated in third clock domain that is an integer multiple of the second clock domain. The user logic interface may include only user-dependent blocks. The physical layer interface may include memory protocol agnostic blocks and/or memory protocol specific blocks. The memory controller may include both memory protocol agnostic blocks and memory protocol dependent blocks. The memory controller may include one or more color pipelines for scheduling memory requests in a parallel arbitration scheme.

公开(公告)号：US10389341B1

公开(公告)日：2019-08-20

申请号：US14981220

申请日：2015-12-28

申请人： ALTERA CORPORATION

发明人： Chee Hak Teh

IPC分类号： H03K5/133 ,  G06F1/10 ,  G06F13/40 ,  H03K5/135 ,  H03K5/00

摘要： One embodiment relates to an integrated circuit with an array of modular physical layer (PHY) slice circuits that are configured into multiple synchronous groups. Each synchronous group receives a delayed synchronous pulse signal provided by a chain of synchronous delay circuits. Another embodiment relates to an array of modular PHY slice circuits, each of which includes a manager circuit that manages the modular PHY slice circuit, a remap circuit that remaps interconnect redundancy, and an input-output module that provides outbound control and data streams and receives inbound control and data streams.

公开(公告)号：US10282109B1

公开(公告)日：2019-05-07

申请号：US15266646

申请日：2016-09-15

申请人： Altera Corporation

发明人： Chee Hak Teh

IPC分类号： G06F3/06 ,  G11C7/10

摘要： An integrated circuit may include memory interface circuitry for communicating with an external or in-package memory module. The integrated circuit may also include out-of-order (OOO) clients and in-order (IO) clients that issue read and write commands to the memory interface circuitry. The memory interface circuitry may include a memory controller having an OOO command scheduler, a write data buffer, and a simple read data pipeline. The memory interface circuitry may also include a multiport arbitration circuit for interfacing with the multiple clients and also OOO adaptor circuits interposed between the multiport arbitration circuit and the IO clients. Each of the OOO adaptor circuits may include an ID generator and a local reordering buffer and may allow the memory controller to return data to the various clients without throttling.

公开(公告)号：US09971733B1

公开(公告)日：2018-05-15

申请号：US14960175

申请日：2015-12-04

申请人： Altera Corporation

发明人： Chee Hak Teh ,  Arifur Rahman

IPC分类号： G06F13/00 ,  G06F13/40 ,  G06F13/38 ,  G06F15/78 ,  G06F1/08 ,  G06F13/42

CPC分类号： G06F15/7803 ,  G06F1/08 ,  G06F13/4022 ,  G06F13/4234 ,  G06F13/4291 ,  G06F15/7864

摘要： A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.

公开(公告)号：US09847783B1

公开(公告)日：2017-12-19

申请号：US14882065

申请日：2015-10-13

申请人： Altera Corporation

发明人： Chee Hak Teh ,  Arifur Rahman ,  Richard Arthur Grenier

IPC分类号： H01L25/00 ,  H03K19/177

CPC分类号： H03K19/1776 ,  H03K19/17736

摘要： A scalable circuit architecture for programmable circuitry is provided. Intellectual property (IP) blocks may be integrated into a circuit design and may be formed next to programmable logic sectors on which user logic functions are implemented. IP blocks may receive configuration data from sub-system managers (SSMs) that serve as a local configuration source for the IP blocks. Configurable endpoints in the IP blocks may be represented by memory mapped addresses that may be decoded by pipeline decoders having delay elements that prevent read data collision. A reroute layer may serve as an interface between IP blocks and one or more programmable logic sectors. The reroute layer may have a higher number of connections at a logic sector interface compared to the number of connections at an IP block interface. An IP block may route clock signals having different frequencies to respective different rows or regions in the programmable logic sectors.

公开(公告)号：US20160098061A1

公开(公告)日：2016-04-07

申请号：US14692133

申请日：2015-04-21

申请人： Altera Corporation

发明人： Chee Hak Teh

IPC分类号： G06F1/08 ,  H03K19/0185 ,  G06F17/50

CPC分类号： H03K19/01855 ,  G06F17/5068

摘要： Systems and methods for interface block. The interface block includes input/output modules distributed along the interface block and a mid-stack module interspersed within the input/output modules. The input/output modules include at least one data module and at least one command module. At least one of the input/output modules is shared by an adjacent pair of channels. Each of the input/output modules is configured to interface with a memory device via a silicon interposer or equivalent. The mid-stack module is in communication with the input/output modules via programmable logic circuitry. The mid-stack module may include independent clock quadrants. Each clock quadrant is configured to operate at different phases where each phase is aligned to a respective core clock.

摘要翻译： 接口块的系统和方法。 接口块包括沿着接口块分布的输入/输出模块和散布在输入/输出模块内的中间堆栈模块。 输入/输出模块包括至少一个数据模块和至少一个命令模块。 至少一个输入/输出模块由相邻的通道对共享。 每个输入/输出模块被配置为经由硅插入器或等同物与存储器件接口。 中间堆栈模块通过可编程逻辑电路与输入/输出模块通信。 中间堆叠模块可以包括独立的时钟象限。 每个时钟象限被配置为在不同的相位工作，其中每个相位与相应的核心时钟对准。

公开(公告)号：US11226925B2

公开(公告)日：2022-01-18

申请号：US16674138

申请日：2019-11-05

申请人： Altera Corporation

发明人： Chee Hak Teh ,  Arifur Rahman

IPC分类号： G06F15/78 ,  G06F13/42 ,  G06F13/40 ,  G06F13/38 ,  G06F13/00 ,  G06F1/06 ,  G06F1/10

摘要： A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.

公开(公告)号：US20210011878A1

公开(公告)日：2021-01-14

申请号：US17037642

申请日：2020-09-29

申请人： Altera Corporation

发明人： Chee Hak Teh ,  Arifur Rahman

IPC分类号： G06F15/78 ,  G06F13/42 ,  G06F13/40 ,  G06F1/06 ,  G06F1/10

摘要： A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.

公开(公告)号：US20200226094A1

公开(公告)日：2020-07-16

申请号：US16833068

申请日：2020-03-27

申请人： Altera Corporation

发明人： Chee Hak Teh ,  Arifur Rahman

IPC分类号： G06F15/78 ,  G06F13/42 ,  G06F13/40 ,  G06F1/06 ,  G06F1/10

摘要： A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.

公开(公告)号：US10482060B2

公开(公告)日：2019-11-19

申请号：US15954078

申请日：2018-04-16

申请人： Altera Corporation

发明人： Chee Hak Teh ,  Arifur Rahman

IPC分类号： G06F13/00 ,  G06F13/40 ,  G06F13/38 ,  G06F15/78 ,  G06F13/42 ,  G06F1/06 ,  G06F1/10

摘要： A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.