公开(公告)号：US09478272B1

公开(公告)日：2016-10-25

申请号：US14245306

申请日：2014-04-04

申请人： Altera Corporation

发明人： Richard Arthur Grenier ,  Michael David Hutton

IPC分类号： G11C8/16 ,  G11C7/00

CPC分类号： G11C8/16 ,  G11C7/00 ,  G11C7/1075

摘要： An integrated circuit may have configurable storage blocks. A configurable storage block may include a memory array and a control circuit. The configurable storage block may receive a mode selection command. The control circuit may determine to operate the configurable storage block in a first mode which may provide random access to the memory array or in a second mode which may provide access to the memory array in a predefined order based on the mode selection command. Thus, the configurable storage block may implement first-in first-cut modules or last-in first-out modules and variations thereof in addition to implementing memory modules with random access.

摘要翻译： 集成电路可以具有可配置的存储块。 可配置存储块可以包括存储器阵列和控制电路。 可配置存储块可以接收模式选择命令。 控制电路可以确定以第一模式操作可配置存储块，该第一模式可以提供对存储器阵列的随机访问或者可以基于模式选择命令以预定义顺序提供对存储器阵列的访问的第二模式。 因此，除了实现具有随机存取的存储器模块之外，可配置存储块可以实现先进先出模块或先进先出模块及其变型。

公开(公告)号：US09847783B1

公开(公告)日：2017-12-19

申请号：US14882065

申请日：2015-10-13

申请人： Altera Corporation

发明人： Chee Hak Teh ,  Arifur Rahman ,  Richard Arthur Grenier

IPC分类号： H01L25/00 ,  H03K19/177

CPC分类号： H03K19/1776 ,  H03K19/17736

摘要： A scalable circuit architecture for programmable circuitry is provided. Intellectual property (IP) blocks may be integrated into a circuit design and may be formed next to programmable logic sectors on which user logic functions are implemented. IP blocks may receive configuration data from sub-system managers (SSMs) that serve as a local configuration source for the IP blocks. Configurable endpoints in the IP blocks may be represented by memory mapped addresses that may be decoded by pipeline decoders having delay elements that prevent read data collision. A reroute layer may serve as an interface between IP blocks and one or more programmable logic sectors. The reroute layer may have a higher number of connections at a logic sector interface compared to the number of connections at an IP block interface. An IP block may route clock signals having different frequencies to respective different rows or regions in the programmable logic sectors.

公开(公告)号：US09218862B1

公开(公告)日：2015-12-22

申请号：US14251423

申请日：2014-04-11

申请人： Altera Corporation

发明人： Richard Arthur Grenier ,  Carl Ebeling

IPC分类号： G11C8/00 ,  G11C8/16 ,  G11C7/18 ,  G11C8/12 ,  G11C11/412 ,  G11C7/10

CPC分类号： G11C8/16 ,  G11C7/1075 ,  G11C7/18 ,  G11C8/06 ,  G11C8/12 ,  G11C11/412

摘要： An integrated circuit may have circuitry that includes a storage circuit, a processing circuit, and at least one state register to implement a finite-state machine. The storage circuit may store base addresses and output data for each state of the finite-state machine. The storage circuit may further store offset values that are based on the input data to the finite-state machine and the state transition from a current state to a next state caused by the input data. The processing circuit may compute the address of the storage circuit location where the output data of the next state is stored. The computation of this address may depend on the offset value and base address of the current state. The state register may receive the address from the processing circuit, store the address, and perform the corresponding memory access operation on the storage circuit.

摘要翻译： 集成电路可以具有包括存储电路，处理电路和用于实现有限状态机的至少一个状态寄存器的电路。 存储电路可以存储有限状态机的每个状态的基地址和输出数据。 存储电路还可以将基于输入数据的偏移值存储到有限状态机，以及由输入数据引起的从当前状态到下一状态的状态转换。 处理电路可以计算存储下一状态的输出数据的存储电路位置的地址。 该地址的计算可能取决于当前状态的偏移值和基址。 状态寄存器可以从处理电路接收地址，存储地址，并在存储电路上执行相应的存储器访问操作。

公开(公告)号：US09106229B1

公开(公告)日：2015-08-11

申请号：US13829965

申请日：2013-03-14

申请人： Altera Corporation

发明人： Michael David Hutton ,  Richard Arthur Grenier

IPC分类号： H03K19/173 ,  G06F17/50

CPC分类号： H03K19/173 ,  G06F17/5077 ,  H01L22/22 ,  H01L23/147 ,  H01L23/5382 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/014

摘要： A multichip package that includes a programmable interposer is provided. Multiple integrated circuits may be mounted on the interposer. Active circuitry may also be embedded in the interposer device to facilitate protocol-based communications, debugging, and other desired circuit operations. The interposer device may include programmable interconnect routing circuitry that serves primarily to provide routing for the different circuits within the multichip package. A design tool may be used to design the interposer device. The design tool may include a standard die footprint library from which standard interface templates can be selected when designing an interposer device that has to communicate various on-interposer integrated circuits. The use of standard die footprints may simplify the design of interposers by enabling a family of devices to interface with a given interposer.

摘要翻译： 提供了一个包含可编程插入器的多芯片封装。 多个集成电路可以安装在插入器上。 有源电路也可以嵌入在插入器装置中以促进基于协议的通信，调试和其它期望的电路操作。 插入器设备可以包括可编程互连路由电路，其主要用于为多芯片封装内的不同电路提供路由。 可以使用设计工具来设计插入器设备。 该设计工具可以包括标准的裸片封装库，当设计必须通信各种内置插件集成电路的插入器装置时，可以从中标准接口模板被选择。 使用标准管芯封装可以通过使一系列器件与给定的插入器接口来简化插入器的设计。