公开(公告)号：US11137983B2

公开(公告)日：2021-10-05

申请号：US16586693

申请日：2019-09-27

申请人： Altera Corporation

发明人： Keone Streicher ,  Martin Langhammer ,  Yi-Wen Lin ,  Hyun Yi

IPC分类号： G06F7/483 ,  G06F7/544 ,  G06F7/485 ,  G06F7/487 ,  G06F7/499

摘要： Configurable specialized processing blocks, such as DSP blocks, are described that implement fixed and floating-point functionality in a single mixed architecture on a programmable device. The described architecture reduces the need to construct floating-point functions outside the configurable specialized processing block, thereby minimizing hardware cost and area. The disclosed architecture also introduces pipelining into the DSP block in order to ensure the floating-point multiplication and addition functions remain in synchronicity, thereby increasing the maximum frequency at which the DSP block can operate. Moreover, the disclosed architecture includes logic circuitry to support floating-point exception handling.

公开(公告)号：US09208357B1

公开(公告)日：2015-12-08

申请号：US14471574

申请日：2014-08-28

申请人： Altera Corporation

发明人： Martin Langhammer ,  Juju Joyce ,  Keone Streicher ,  David Jefferson ,  Srinivas Reddy ,  Nitin Prasad

IPC分类号： G06F21/00 ,  G06F21/76 ,  H04L9/06 ,  H04L9/14 ,  G06F21/60

CPC分类号： H04L9/065 ,  G06F21/60 ,  G06F21/76 ,  H04L9/0877 ,  H04L9/14 ,  H04L2209/12 ,  H04L2209/16 ,  H04L2209/26

摘要： Circuits, methods, and apparatus that prevent detection and erasure of encoding or encryption keys. These encoding keys may be used to encode a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a first key to form an encoding key in order to prevent detection of the first key. In a specific embodiment, the first key is encoded using a second key. The encoded key is used to encode a configuration bitstream or other data. The encoded key is stored on an FPGA or other device. When the device is to be configured, the encoded key is retrieved and used to decode the bitstream or other data. A further embodiment stores an encryption key in a one-time programmable memory (OTP) array to prevent its erasure or modification. The encoding key may be further obfuscated before storage.

摘要翻译： 阻止检测和擦除编码或加密密钥的电路，方法和装置。 这些编码密钥可以用于对配置比特流或FPGA或其他设备的其他数据进行编码。 本发明的示例性实施例掩蔽第一密钥以形成编码密钥，以便防止第一密钥的检测。 在具体实施例中，使用第二密钥对第一密钥进行编码。 编码密钥用于对配置比特流或其他数据进行编码。 编码密钥存储在FPGA或其他设备上。 当要配置设备时，将检索编码密钥并将其用于解码比特流或其他数据。 另一实施例将加密密钥存储在一次性可编程存储器（OTP）阵列中以防止其擦除或修改。 在存储之前可以进一步模糊编码密钥。

公开(公告)号：US08750503B1

公开(公告)日：2014-06-10

申请号：US13750360

申请日：2013-01-25

申请人： Altera Corporation

发明人： Keone Streicher ,  David Jefferson ,  Juju Joyce ,  Martin Langhammer

IPC分类号： H04L9/00

CPC分类号： H04L9/0822 ,  H04L9/0631 ,  H04L9/065 ,  H04L9/0861 ,  H04L2209/24

摘要： Circuits, methods, and apparatus that prevent detection and erasure of a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a user key in order to prevent its detection. In a specific embodiment, the user key is masked by software that performs a function on it a first number of times. The result is used to encrypt a configuration bitstream. The user key is also provided to an FPGA or other device, where the function is performed a second number of times and the result stored. When the device is configured, the result is retrieved, the function is performed on it the first number of times less the second number of times and then it is used to decrypt the configuration bitstream. A further embodiment uses a one-time programmable fuse (OTP) array to prevent erasure or modification.

摘要翻译： 阻止对FPGA或其他设备的配置比特流或其他数据的检测和擦除的电路，方法和装置。 本发明的示例性实施例掩盖用户密钥以防止其检测。 在具体实施例中，用户密钥被第一次执行功能的软件掩码。 结果用于加密配置比特流。 用户密钥还提供给FPGA或其他设备，其中功能被执行第二次并且存储结果。 当配置设备时，将检索结果，该功能在其上执行第一次次数少于第二次，然后用于解密配置比特流。 另一实施例使用一次性可编程熔丝（OTP）阵列来防止擦除或修改。

公开(公告)号：US20130332497A1

公开(公告)日：2013-12-12

申请号：US13961534

申请日：2013-08-07

申请人： Altera Corporation

发明人： Keone Streicher ,  Martin Langhammer ,  Yi-Wen Lin ,  Wai-Bor Leung ,  David Lewis ,  Volker Mauer ,  Henry Y. Lui ,  Suleyman Sirri Demirsoy ,  Hyun Yi

IPC分类号： G06F17/10

CPC分类号： G06F17/10 ,  G06F7/5324 ,  G06F2207/382 ,  H03H17/06 ,  H03H2220/06 ,  H03K19/17732

摘要： Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.

摘要翻译： 提供数字信号处理（“DSP”）电路块，如果需要，可以更容易地一起工作来执行更大（例如更复杂和/或更具有算术精度）的DSP操作。 尽管不能使用某些块（例如，由于电路缺陷），这些DSP块还可以包括有助于将多个这样的块拼接在一起的冗余电路。 收缩寄存器可以包括在DSP块中的各个点处，以便于使用块来实现收缩形式，有限脉冲响应（“FIR”），数字滤波器。

公开(公告)号：US20140082035A1

公开(公告)日：2014-03-20

申请号：US14086328

申请日：2013-11-21

申请人： Altera Corporation

发明人： Keone Streicher ,  Martin Langhammer ,  Yi-Wen Lin ,  Wai-Bor Leung ,  David Lewis ,  Volker Mauer ,  Henry Y. Lui ,  Suleyman Sirri Demirsoy ,  Hyun Yi

IPC分类号： G06F17/10

CPC分类号： G06F17/10 ,  G06F7/5324 ,  G06F2207/382 ,  H03H17/06 ,  H03H2220/06 ,  H03K19/17732

摘要： Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.

摘要翻译： 提供数字信号处理（“DSP”）电路块，如果需要，可以更容易地一起工作来执行更大（例如更复杂和/或更具有算术精度）的DSP操作。 尽管不能使用某些块（例如，由于电路缺陷），这些DSP块还可以包括有助于将多个这样的块拼接在一起的冗余电路。 收缩寄存器可以包括在DSP块中的各个点处，以便于使用块来实现收缩形式，有限脉冲响应（“FIR”），数字滤波器。

公开(公告)号：US20220027128A1

公开(公告)日：2022-01-27

申请号：US17493584

申请日：2021-10-04

申请人： Altera Corporation

发明人： Keone Streicher ,  Martin Langhammer ,  Yi-Wen Lin ,  Hyun Yi

IPC分类号： G06F7/485 ,  G06F7/487 ,  G06F7/499 ,  G06F7/483 ,  G06F7/544

摘要： Configurable specialized processing blocks, such as DSP blocks, are described that implement fixed and floating-point functionality in a single mixed architecture on a programmable device. The described architecture reduces the need to construct floating-point functions outside the configurable specialized processing block, thereby minimizing hardware cost and area. The disclosed architecture also introduces pipelining into the DSP block in order to ensure the floating-point multiplication and addition functions remain in synchronicity, thereby increasing the maximum frequency at which the DSP block can operate. Moreover, the disclosed architecture includes logic circuitry to support floating-point exception handling.

公开(公告)号：US20200026493A1

公开(公告)日：2020-01-23

申请号：US16586693

申请日：2019-09-27

申请人： Altera Corporation

发明人： Keone Streicher ,  Martin Langhammer ,  Yi-Wen Lin ,  Hyun Yi

IPC分类号： G06F7/483 ,  G06F7/487 ,  G06F7/485 ,  G06F7/499

摘要： Configurable specialized processing blocks, such as DSP blocks, are described that implement fixed and floating-point functionality in a single mixed architecture on a programmable device. The described architecture reduces the need to construct floating-point functions outside the configurable specialized processing block, thereby minimizing hardware cost and area. The disclosed architecture also introduces pipelining into the DSP block in order to ensure the floating-point multiplication and addition functions remain in synchronicity, thereby increasing the maximum frequency at which the DSP block can operate. Moreover, the disclosed architecture includes logic circuitry to support floating-point exception handling.

公开(公告)号：US10474429B1

公开(公告)日：2019-11-12

申请号：US15331024

申请日：2016-10-21

申请人： Altera Corporation

发明人： Keone Streicher ,  Martin Langhammer ,  Yi-Wen Lin ,  Hyun Yi

IPC分类号： G06F7/483 ,  G06F7/485 ,  G06F7/487 ,  G06F7/499

摘要： Configurable specialized processing blocks, such as DSP blocks, are described that implement fixed and floating-point functionality in a single mixed architecture on a programmable device. The described architecture reduces the need to construct floating-point functions outside the configurable specialized processing block, thereby minimizing hardware cost and area. The disclosed architecture also introduces pipelining into the DSP block in order to ensure the floating-point multiplication and addition functions remain in synchronicity, thereby increasing the maximum frequency at which the DSP block can operate. Moreover, the disclosed architecture includes logic circuitry to support floating-point exception handling.

公开(公告)号：US09507565B1

公开(公告)日：2016-11-29

申请号：US14180664

申请日：2014-02-14

申请人： Altera Corporation

发明人： Keone Streicher ,  Martin Langhammer ,  Yi-Wen Lin ,  Hyun Yi

IPC分类号： G06F7/483 ,  G06F7/499 ,  G06F7/485 ,  G06F7/487

CPC分类号： G06F7/485 ,  G06F7/483 ,  G06F7/4876 ,  G06F7/499

摘要： Configurable specialized processing blocks, such as DSP blocks, are described that implement fixed and floating-point functionality in a single mixed architecture on a programmable device. The described architecture reduces the need to construct floating-point functions outside the configurable specialized processing block, thereby minimizing hardware cost and area. The disclosed architecture also introduces pipelining into the DSP block in order to ensure the floating-point multiplication and addition functions remain in synchronicity, thereby increasing the maximum frequency at which the DSP block can operate. Moreover, the disclosed architecture includes logic circuitry to support floating-point exception handling.

摘要翻译： 描述了可配置的专用处理块，例如DSP块，其在可编程设备上的单个混合架构中实现固定和浮点功能。 所描述的架构减少了在可配置专用处理块之外构建浮点函数的需要，从而最小化硬件成本和面积。 所公开的架构还将流水线引入到DSP模块中，以确保浮点乘法和加法函数保持同步，从而增加DSP块可以工作的最大频率。 此外，所公开的架构包括支持浮点异常处理的逻辑电路。

公开(公告)号：US09054859B1

公开(公告)日：2015-06-09

申请号：US14265117

申请日：2014-04-29

申请人： Altera Corporation

发明人： Keone Streicher ,  David Jefferson ,  Juju Joyce ,  Martin Langhammer

IPC分类号： H04L29/06 ,  G06F15/16 ,  H04L9/08

CPC分类号： H04L9/0822 ,  H04L9/0631 ,  H04L9/065 ,  H04L9/0861 ,  H04L2209/24

摘要： Circuits, methods, and apparatus that prevent detection and erasure of a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a user key in order to prevent its detection. In a specific embodiment, the user key is masked by software that performs a function on it a first number of times. The result is used to encrypt a configuration bitstream. The user key is also provided to an FPGA or other device, where the function is performed a second number of times and the result stored. When the device is configured, the result is retrieved, the function is performed on it the first number of times less the second number of times and then it is used to decrypt the configuration bitstream. A further embodiment uses a one-time programmable fuse (OTP) array to prevent erasure or modification.