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1.发明申请SERIALIZER CIRCUITRY FOR HIGH-SPEED SERIAL DATA TRANSMITTERS ON PROGRAMMABLE LOGIC DEVICE INTEGRATED CIRCUITS 审中-公开用于可编程逻辑器件集成电路的高速串行数据传输器的串行电路公开(公告)号：US20140009188A1
公开(公告)日：2014-01-09
申请号：US14022639
申请日：2013-09-10
申请人： Altera Corporation
发明人： Toan Thanh Nguyen , Thungoc M. Tran , Sergey Shumarayev , Arch Zaliznyak , Shoujun Wang , Ramanand Venkata , Chong H. Lee
IPC分类号： H03K19/00
CPC分类号： H03K19/00 , H03K19/17744 , H03M9/00 , H04L1/243 , H04L7/0008 , H04L7/033 , H04L25/0266
摘要： Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).
摘要翻译： 用于可编程逻辑器件（“PLD”）等上的高速串行数据发射器电路的串行器电路包括用于将具有若干数据宽度中的任一个的并行数据转换为串行数据的电路。 电路还可以在宽频率范围内的任何频率下操作，并且可以利用具有与并行数据速率和/或串行数据速率的几个关系中的任何一个的参考时钟信号。 该电路在各个方面是可配置的/可重新配置的，其中至少一些配置/重新配置可被动态地控制（即在PLD的用户模式操作期间）。
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2.发明授权Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits 有权用于可编程逻辑器件集成电路上的高速串行数据发射器的串行器电路公开(公告)号：US09077330B2
公开(公告)日：2015-07-07
申请号：US14022639
申请日：2013-09-10
申请人： Altera Corporation
发明人： Toan Thanh Nguyen , Thungoc M. Tran , Sergey Shumarayev , Arch Zaliznyak , Shoujun Wang , Ramanand Venkata , Chong H. Lee
CPC分类号： H03K19/00 , H03K19/17744 , H03M9/00 , H04L1/243 , H04L7/0008 , H04L7/033 , H04L25/0266
摘要： Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).
摘要翻译： 用于可编程逻辑器件（“PLD”）等上的高速串行数据发射器电路的串行器电路包括用于将具有若干数据宽度中的任一个的并行数据转换为串行数据的电路。 电路还可以在宽频率范围内的任何频率下操作，并且可以利用具有与并行数据速率和/或串行数据速率的几个关系中的任何一个的参考时钟信号。 该电路在各个方面是可配置的/可重新配置的，其中至少一些配置/重新配置可被动态地控制（即在PLD的用户模式操作期间）。
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