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    SERIALIZER CIRCUITRY FOR HIGH-SPEED SERIAL DATA TRANSMITTERS ON PROGRAMMABLE LOGIC DEVICE INTEGRATED CIRCUITS
    2.
    发明申请
    SERIALIZER CIRCUITRY FOR HIGH-SPEED SERIAL DATA TRANSMITTERS ON PROGRAMMABLE LOGIC DEVICE INTEGRATED CIRCUITS 审中-公开
    用于可编程逻辑器件集成电路的高速串行数据传输器的串行电路

    公开(公告)号：US20140009188A1

    公开(公告)日：2014-01-09

    申请号：US14022639

    申请日：2013-09-10

    申请人： Altera Corporation

    发明人： Toan Thanh Nguyen ,  Thungoc M. Tran ,  Sergey Shumarayev ,  Arch Zaliznyak ,  Shoujun Wang ,  Ramanand Venkata ,  Chong H. Lee

    IPC分类号： H03K19/00

    CPC分类号： H03K19/00 ,  H03K19/17744 ,  H03M9/00 ,  H04L1/243 ,  H04L7/0008 ,  H04L7/033 ,  H04L25/0266

    摘要： Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).

    摘要翻译： 用于可编程逻辑器件（“PLD”）等上的高速串行数据发射器电路的串行器电路包括用于将具有若干数据宽度中的任一个的并行数据转换为串行数据的电路。 电路还可以在宽频率范围内的任何频率下操作，并且可以利用具有与并行数据速率和/或串行数据速率的几个关系中的任何一个的参考时钟信号。 该电路在各个方面是可配置的/可重新配置的，其中至少一些配置/重新配置可被动态地控制（即在PLD的用户模式操作期间）。

    Heterogeneous high-speed serial interface system with phase-locked loop architecture and clock distribution system
    6.
    发明授权
    Heterogeneous high-speed serial interface system with phase-locked loop architecture and clock distribution system 有权
    具有锁相环架构和时钟分配系统的异构高速串行接口系统

    公开(公告)号：US08700825B1

    公开(公告)日：2014-04-15

    申请号：US13679061

    申请日：2012-11-16

    申请人： Altera Corporation

    发明人： Surinder Singh ,  Wai-Bor Leung ,  Henry Y. Lui ,  Arch Zaliznyak

    IPC分类号： G06F3/00 ,  H03L7/06 ,  H03K19/173 ,  G06F5/00

    CPC分类号： H03K19/017581 ,  H03K19/17776 ,  H03L7/183 ,  H03L7/23

    摘要： One embodiment relates to an integrated circuit having a plurality of four-channel serial interface modules. Each of the plurality of four-channel serial interface modules includes a first physical medium attachment (PMA) channel circuit, a second PMA channel circuit adjacent to the first PMA channel circuit, a third PMA channel circuit adjacent to the second PMA channel circuit, a fourth PMA channel circuit adjacent to the third PMA channel circuit, and at least one phase-locked loop (PLL) circuit which is programmably coupled to each of the first, second, third and fourth PMA channel circuits. Other embodiments and features are also disclosed.

    摘要翻译： 一个实施例涉及具有多个四通道串行接口模块的集成电路。 多个四通道串行接口模块中的每一个包括第一物理介质连接（PMA）信道电路，与第一PMA信道电路相邻的第二PMA信道电路，与第二PMA信道电路相邻的第三PMA信道电路， 与第三PMA通道电路相邻的第四PMA通道电路，以及可编程地耦合到第一，第二，第三和第四PMA通道电路中的每一个的至少一个锁相环（PLL）电路。 还公开了其它实施例和特征。