公开(公告)号：US08586425B2

公开(公告)日：2013-11-19

申请号：US12964747

申请日：2010-12-10

申请人： An-Thung Cho ,  Wan-Yi Liu ,  Chia-Kai Chen ,  Wu-Hsiung Lin ,  Chun-Hsiun Chen ,  Wei-Ming Huang

发明人： An-Thung Cho ,  Wan-Yi Liu ,  Chia-Kai Chen ,  Wu-Hsiung Lin ,  Chun-Hsiun Chen ,  Wei-Ming Huang

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L29/78651 ,  H01L21/02532 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/02686 ,  H01L29/66068 ,  H01L29/66969 ,  H01L29/78684 ,  H01L29/7869

摘要： A thin film transistor disposed on a substrate is provided. The thin film transistor includes a gate, a gate insulating layer, a silicon-rich channel layer, a source, and a drain. The gate is disposed on the substrate. The gate insulator is disposed over the gate. The silicon-rich channel layer is disposed above the gate, wherein the material of the silicon-rich channel layer is selected from a group consisting of silicon-rich silicon oxide (Si-rich SiOx), silicon-rich silicon nitride (Si-rich SiNx), silicon-rich silicon oxynitride (Si-rich SiOxNy), silicon-rich silicon carbide (Si-rich SiC) and silicon-rich silicon oxycarbide (Si-rich SiOC). The content (concentration) of silicon of the silicon-rich channel layer within a film depth between 10 nm to 170 nm ranges from about 1E23 atoms/cm3 to about 4E23 atoms/cm3. The source and the drain are connected with the silicon-rich channel layer.

摘要翻译： 设置在基板上的薄膜晶体管。 薄膜晶体管包括栅极，栅极绝缘层，富硅沟道层，源极和漏极。 栅极设置在基板上。 栅极绝缘体设置在栅极上。 富硅沟道层设置在栅极上方，其中富硅沟道层的材料选自富硅氧化硅（富Si），富含硅的氮化硅（富Si） SiN x），富硅氧氮化硅（富Si的SiO x N y），富含硅的碳化硅（富Si的SiC）和富硅的碳氧化碳（富Si的SiOC）。 在10nm至170nm的膜深度内的富硅沟道层的硅含量（浓度）范围为约1E23原子/ cm3至约4E23原子/ cm3。 源极和漏极与富硅沟道层连接。

公开(公告)号：US20110156043A1

公开(公告)日：2011-06-30

申请号：US12964747

申请日：2010-12-10

申请人： An-Thung Cho ,  Wan-Yi Liu ,  Chia-Kai Chen ,  Wu-Hsiung Lin ,  Chun-Hsiun Chen ,  Wei-Ming Huang

发明人： An-Thung Cho ,  Wan-Yi Liu ,  Chia-Kai Chen ,  Wu-Hsiung Lin ,  Chun-Hsiun Chen ,  Wei-Ming Huang

IPC分类号： H01L29/786 ,  H01L21/268 ,  H01L21/205

CPC分类号： H01L29/78651 ,  H01L21/02532 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/02686 ,  H01L29/66068 ,  H01L29/66969 ,  H01L29/78684 ,  H01L29/7869

摘要： A thin film transistor disposed on a substrate is provided. The thin film transistor includes a gate, a gate insulating layer, a silicon-rich channel layer, a source, and a drain. The gate is disposed on the substrate. The gate insulator is disposed over the gate. The silicon-rich channel layer is disposed above the gate, wherein the material of the silicon-rich channel layer is selected from a group consisting of silicon-rich silicon oxide (Si-rich SiOx), silicon-rich silicon nitride (Si-rich SiNx), silicon-rich silicon oxynitride (Si-rich SiOxNy), silicon-rich silicon carbide (Si-rich SiC) and silicon-rich silicon oxycarbide (Si-rich SiOC). The content (concentration) of silicon of the silicon-rich channel layer within a film depth between 10 nm to 170 nm ranges from about 1E23 atoms/cm3 to about 4E23 atoms/cm3. The source and the drain are connected with the silicon-rich channel layer.

摘要翻译： 设置在基板上的薄膜晶体管。 薄膜晶体管包括栅极，栅极绝缘层，富硅沟道层，源极和漏极。 栅极设置在基板上。 栅极绝缘体设置在栅极上。 富硅沟道层设置在栅极上方，其中富硅沟道层的材料选自富硅氧化硅（富Si），富含硅的氮化硅（富Si） SiN x），富硅氧氮化硅（富Si的SiO x N y），富含硅的碳化硅（富Si的SiC）和富硅的碳氧化碳（富Si的SiOC）。 在10nm至170nm的膜深度内的富硅沟道层的硅含量（浓度）范围为约1E23原子/ cm3至约4E23原子/ cm3。 源极和漏极与富硅沟道层连接。

公开(公告)号：US20140084291A1

公开(公告)日：2014-03-27

申请号：US13625949

申请日：2012-09-25

申请人： Jia-Hong YE ,  Ssu-Hui Lu ,  Wu-Hsiung Lin ,  Chao-Chien Chiu ,  Ming-Hsien Lee ,  Chia-Tien Peng ,  Wei-Ming Huang

发明人： Jia-Hong YE ,  Ssu-Hui Lu ,  Wu-Hsiung Lin ,  Chao-Chien Chiu ,  Ming-Hsien Lee ,  Chia-Tien Peng ,  Wei-Ming Huang

IPC分类号： H01L29/04 ,  H01L21/336 ,  H01L29/786

CPC分类号： H01L27/1255 ,  H01L27/1218 ,  H01L27/1248 ,  H01L29/78603

摘要： An active device array substrate includes a flexible substrate, a gate electrode, a dielectric layer, a channel layer, a source electrode, a drain electrode, and a pixel electrode. The flexible substrate has at least one transistor region and at least one transparent region adjacent to each other. The gate electrode is disposed on the transistor region of the flexible substrate. The dielectric layer covers the flexible substrate and the gate electrode. A portion of the dielectric layer disposed on the gate electrode has a first thickness. Another portion of the dielectric layer disposed on the transparent region of the flexible substrate has a second thickness. The second thickness is less than the first thickness. The channel layer is disposed above the gate electrode. The source electrode and the drain electrode are disposed on opposite sides of the channel layer and are electrically connected to the channel layer.

摘要翻译： 有源器件阵列衬底包括柔性衬底，栅电极，电介质层，沟道层，源电极，漏电极和像素电极。 柔性基板具有至少一个晶体管区域和至少一个彼此相邻的透明区域。 栅电极设置在柔性基板的晶体管区域上。 电介质层覆盖柔性基板和栅电极。 布置在栅电极上的介电层的一部分具有第一厚度。 设置在柔性基板的透明区域上的介电层的另一部分具有第二厚度。 第二厚度小于第一厚度。 沟道层设置在栅电极的上方。 源电极和漏极设置在沟道层的相对侧上并且电连接到沟道层。

公开(公告)号：US08377760B2

公开(公告)日：2013-02-19

申请号：US13338262

申请日：2011-12-28

申请人： Wu-Hsiung Lin ,  Ming-Wei Sun

发明人： Wu-Hsiung Lin ,  Ming-Wei Sun

IPC分类号： H01L21/00

CPC分类号： H01L29/7869

摘要： A TFT including a gate, a gate insulation layer, an oxide semiconductor layer, a translucent layer, a source, and a drain. The gate insulation layer covers the gate. The oxide semiconductor layer is disposed on the gate insulation layer and located above the gate. The oxide semiconductor layer includes an oxide channel layer and two ohmic contact layers. The ohmic contact layers are respectively located beside the oxide channel layer and connected with the oxide channel layer. The translucent layer is located above the oxide channel layer. The source and the drain are disposed on the gate insulation layer and the ohmic contact layers. The source and the drain are electrically insulated from each other.

摘要翻译： 包括栅极，栅极绝缘层，氧化物半导体层，半透明层，源极和漏极的TFT。 栅极绝缘层覆盖栅极。 氧化物半导体层设置在栅极绝缘层上并位于栅极上方。 氧化物半导体层包括氧化物沟道层和两个欧姆接触层。 欧姆接触层分别位于氧化物沟道层旁边并与氧化物沟道层相连。 半透明层位于氧化物通道层的上方。 源极和漏极设置在栅极绝缘层和欧姆接触层上。 源极和漏极彼此电绝缘。

公开(公告)号：US20120138932A1

公开(公告)日：2012-06-07

申请号：US13089298

申请日：2011-04-18

申请人： Wu-Hsiung Lin ,  Po-Hsueh Chen ,  Shin-Shueh Chen ,  Guang-Ren Shen ,  Jia-Hong Ye

发明人： Wu-Hsiung Lin ,  Po-Hsueh Chen ,  Shin-Shueh Chen ,  Guang-Ren Shen ,  Jia-Hong Ye

IPC分类号： H01L29/04

CPC分类号： H01L27/1255 ,  G02F1/136213 ,  G02F2201/40 ,  G02F2202/10 ,  G02F2203/01 ,  H01L27/1225 ,  H01L29/41733 ,  H01L29/7869

摘要： A pixel structure and a manufacturing method thereof are provided. In the pixel structure, an electrode of a storage capacitor is formed when an active layer is formed, and the electrode and the active layer are made of the same material. The material of the electrode and the active layer can be an oxide semiconductor with high transmittance. Therefore, a stable display frame of the pixel structure can be provided by the storage capacitor, an aperture ratio of the pixel structure can be improved, and power consumption can be further reduced.

摘要翻译： 提供像素结构及其制造方法。 在像素结构中，当形成有源层时形成存储电容器的电极，并且电极和有源层由相同的材料制成。 电极和有源层的材料可以是具有高透射率的氧化物半导体。 因此，可以通过存储电容器提供像素结构的稳定的显示框，可以提高像素结构的开口率，并且能够进一步降低功耗。

公开(公告)号：US08674350B2

公开(公告)日：2014-03-18

申请号：US13284961

申请日：2011-10-30

申请人： Chung-Tao Chen ,  Wu-Hsiung Lin ,  Po-Hsueh Chen

发明人： Chung-Tao Chen ,  Wu-Hsiung Lin ,  Po-Hsueh Chen

IPC分类号： H01L29/10

CPC分类号： H01L29/66765 ,  H01L29/41733 ,  H01L29/78606 ,  H01L29/7869

摘要： A thin film transistor (TFT) includes a gate electrode, a gate insulating layer, a first protective pattern, a second protective pattern, a source electrode, a drain electrode, a semiconductor channel layer, and a passivation layer. The first protective pattern and the second protective pattern are disposed on the gate insulating layer above the gate electrode. The source electrode is disposed on the gate insulating layer and the first protective pattern. The drain electrode is disposed on the gate insulating layer and the second protective pattern. The semiconductor channel layer is disposed on the gate insulating layer, the source electrode, and the drain electrode. In an extending direction from the source electrode to the drain electrode, a length of the first protective pattern is shorter than that of the source electrode, and a length of the second protective pattern is shorter than that of the drain electrode.

摘要翻译： 薄膜晶体管（TFT）包括栅电极，栅极绝缘层，第一保护图案，第二保护图案，源电极，漏电极，半导体沟道层和钝化层。 第一保护图案和第二保护图案设置在栅极电极上方的栅极绝缘层上。 源电极设置在栅绝缘层和第一保护图案上。 漏电极设置在栅绝缘层和第二保护图案上。 半导体沟道层设置在栅绝缘层，源电极和漏电极上。 在从源电极到漏电极的延伸方向上，第一保护图案的长度短于源电极的长度，并且第二保护图案的长度短于漏电极的长度。

公开(公告)号：US08604477B2

公开(公告)日：2013-12-10

申请号：US13089298

申请日：2011-04-18

申请人： Wu-Hsiung Lin ,  Po-Hsueh Chen ,  Shin-Shueh Chen ,  Guang-Ren Shen ,  Jia-Hong Ye

发明人： Wu-Hsiung Lin ,  Po-Hsueh Chen ,  Shin-Shueh Chen ,  Guang-Ren Shen ,  Jia-Hong Ye

IPC分类号： H01L29/04 ,  H01L29/10 ,  H01L31/00

CPC分类号： H01L27/1255 ,  G02F1/136213 ,  G02F2201/40 ,  G02F2202/10 ,  G02F2203/01 ,  H01L27/1225 ,  H01L29/41733 ,  H01L29/7869

摘要： A pixel structure and a manufacturing method thereof are provided. In the pixel structure, an electrode of a storage capacitor is formed when an active layer is formed, and the electrode and the active layer are made of the same material. The material of the electrode and the active layer can be an oxide semiconductor with high transmittance. Therefore, a stable display frame of the pixel structure can be provided by the storage capacitor, an aperture ratio of the pixel structure can be improved, and power consumption can be further reduced.

摘要翻译： 提供像素结构及其制造方法。 在像素结构中，当形成有源层时形成存储电容器的电极，并且电极和有源层由相同的材料制成。 电极和有源层的材料可以是具有高透射率的氧化物半导体。 因此，可以通过存储电容器提供像素结构的稳定的显示框，可以提高像素结构的开口率，并且能够进一步降低功耗。

公开(公告)号：US20130049002A1

公开(公告)日：2013-02-28

申请号：US13284961

申请日：2011-10-30

申请人： Chung-Tao Chen ,  Wu-Hsiung Lin ,  Po-Hsueh Chen

发明人： Chung-Tao Chen ,  Wu-Hsiung Lin ,  Po-Hsueh Chen

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/66765 ,  H01L29/41733 ,  H01L29/78606 ,  H01L29/7869

摘要： A thin film transistor (TFT) includes a gate electrode, a gate insulating layer, a first protective pattern, a second protective pattern, a source electrode, a drain electrode, a semiconductor channel layer, and a passivation layer. The first protective pattern and the second protective pattern are disposed on the gate insulating layer above the gate electrode. The source electrode is disposed on the gate insulating layer and the first protective pattern. The drain electrode is disposed on the gate insulating layer and the second protective pattern. The semiconductor channel layer is disposed on the gate insulating layer, the source electrode, and the drain electrode. In an extending direction from the source electrode to the drain electrode, a length of the first protective pattern is shorter than that of the source electrode, and a length of the second protective pattern is shorter than that of the drain electrode.

摘要翻译： 薄膜晶体管（TFT）包括栅电极，栅极绝缘层，第一保护图案，第二保护图案，源电极，漏电极，半导体沟道层和钝化层。 第一保护图案和第二保护图案设置在栅极电极上方的栅极绝缘层上。 源电极设置在栅绝缘层和第一保护图案上。 漏电极设置在栅绝缘层和第二保护图案上。 半导体沟道层设置在栅绝缘层，源电极和漏电极上。 在从源电极到漏电极的延伸方向上，第一保护图案的长度短于源电极的长度，并且第二保护图案的长度短于漏电极的长度。

公开(公告)号：US08119465B1

公开(公告)日：2012-02-21

申请号：US13041439

申请日：2011-03-07

申请人： Wu-Hsiung Lin ,  Ming-Wei Sun

发明人： Wu-Hsiung Lin ,  Ming-Wei Sun

IPC分类号： H01L21/00

CPC分类号： H01L29/7869

摘要： A method of fabricating a thin film transistor including: forming a gate on a substrate; forming a gate insulation layer on the substrate to cover the gate; forming an oxide semiconductor layer on the gate insulation layer; forming a translucent layer on a partial region of the oxide semiconductor layer; performing an optical annealing process to transform the oxide semiconductor layer into an oxide channel layer and two ohmic contact layers by using the translucent layer as a mask, where the oxide channel layer is located under the translucent layer, and the ohmic contact layers are respectively located beside the oxide channel layer and are connected with the oxide channel layer; and forming a source and a drain electrically insulated from each other on the gate insulation layer and the ohmic contact layers.

摘要翻译： 一种制造薄膜晶体管的方法，包括：在衬底上形成栅极; 在所述基板上形成栅极绝缘层以覆盖所述栅极; 在所述栅极绝缘层上形成氧化物半导体层; 在所述氧化物半导体层的部分区域上形成半透明层; 通过使用半透明层作为掩模将氧化物半导体层转变为氧化物沟道层和两个欧姆接触层，其中氧化物沟道层位于透光层下方，并且欧姆接触层分别位于 在氧化物沟道层旁边并与氧化物沟道层连接; 以及在栅极绝缘层和欧姆接触层上形成彼此电绝缘的源极和漏极。

公开(公告)号：US20120097943A1

公开(公告)日：2012-04-26

申请号：US13338262

申请日：2011-12-28

申请人： Wu-Hsiung Lin ,  Ming-Wei Sun

发明人： Wu-Hsiung Lin ,  Ming-Wei Sun

IPC分类号： H01L29/786

CPC分类号： H01L29/7869

摘要： A TFT including a gate, a gate insulation layer, an oxide semiconductor layer, a translucent layer, a source, and a drain. The gate insulation layer covers the gate. The oxide semiconductor layer is disposed on the gate insulation layer and located above the gate. The oxide semiconductor layer includes an oxide channel layer and two ohmic contact layers. The ohmic contact layers are respectively located beside the oxide channel layer and connected with the oxide channel layer. The translucent layer is located above the oxide channel layer. The source and the drain are disposed on the gate insulation layer and the ohmic contact layers. The source and the drain are electrically insulated from each other.

摘要翻译： 包括栅极，栅极绝缘层，氧化物半导体层，半透明层，源极和漏极的TFT。 栅极绝缘层覆盖栅极。 氧化物半导体层设置在栅极绝缘层上并位于栅极上方。 氧化物半导体层包括氧化物沟道层和两个欧姆接触层。 欧姆接触层分别位于氧化物沟道层旁边并与氧化物沟道层相连。 半透明层位于氧化物通道层的上方。 源极和漏极设置在栅极绝缘层和欧姆接触层上。 源极和漏极彼此电绝缘。