OPTICAL MEASUREMENT OF DISPLACEMENT
    1.
    发明申请

    公开(公告)号:US20190339390A1

    公开(公告)日:2019-11-07

    申请号:US16375551

    申请日:2019-04-04

    Abstract: Systems and methods for optically measuring displacement of an element include an emitter for emitting an optical signal, a first detector for detecting reflections of the optical signal from the element, a second detector for detecting reflections of the optical signal from a raised cover structure, a processor for receiving the detected reflections from the first and second detectors and removing distortions in the detected reflections from the first detector using the detected reflections from the second detector.

    TWO-WIRE COMMUNICATION SYSTEMS AND APPLICATIONS

    公开(公告)号:US20200257646A1

    公开(公告)日:2020-08-13

    申请号:US16859611

    申请日:2020-04-27

    Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

    TWO-WIRE COMMUNICATION SYSTEMS AND APPLICATIONS

    公开(公告)号:US20220156219A1

    公开(公告)日:2022-05-19

    申请号:US17589715

    申请日:2022-01-31

    Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

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