公开(公告)号：US20220156219A1

公开(公告)日：2022-05-19

申请号：US17589715

申请日：2022-01-31

Applicant: Analog Devices, Inc.

Inventor： Martin KESSLER ,  Miguel A. CHAVEZ ,  Lewis F. LAHR ,  William HOOPER ,  Robert Adams ,  Peter SEALEY

IPC: G06F13/42 ,  G05B19/418 ,  G06F1/26 ,  H04B3/54 ,  G05B19/042 ,  H04L12/403 ,  G06F13/364

Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

公开(公告)号：US20200257646A1

公开(公告)日：2020-08-13

申请号：US16859611

申请日：2020-04-27

Applicant: Analog Devices, Inc.

Inventor： Martin KESSLER ,  Miguel A. CHAVEZ ,  Lewis F. LAHR ,  William HOOPER ,  Robert Adams ,  Peter SEALEY

IPC: G06F13/42 ,  G06F13/364 ,  H04L12/403 ,  H04B3/54 ,  G06F1/26 ,  G05B19/042 ,  G05B19/418

Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

公开(公告)号：US20190278733A1

公开(公告)日：2019-09-12

申请号：US16427131

申请日：2019-05-30

Applicant: Analog Devices, Inc.

Inventor： Martin KESSLER ,  Miguel CHAVEZ ,  Lewis F. LAHR ,  William HOOPER ,  Robert Adams ,  Peter SEALEY

IPC: G06F13/42 ,  G06F13/364 ,  G05B19/418 ,  G06F1/26 ,  H04B3/54 ,  G05B19/042 ,  H04L12/403

Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.