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    ETHERNET FRAME COMMUNICATION OVER SYNCHRONOUS COMMUNICATION NETWORK
    1.
    发明申请
    ETHERNET FRAME COMMUNICATION OVER SYNCHRONOUS COMMUNICATION NETWORK 有权

    公开(公告)号：US20250096994A1

    公开(公告)日：2025-03-20

    申请号：US18468395

    申请日：2023-09-15

    Applicant: Analog Devices, Inc.

    Inventor： Martin KESSLER ,  Neelamegam SUBRAMANI ,  Lewis F. LAHR

    IPC: H04L5/14 ,  H04L12/40

    Abstract: A communication system includes a plurality of nodes connected in a daisy-chain via respective bus links. The plurality of nodes are configured for full-duplex, synchronized communication over the bus links for transmission of Ethernet frames within a flexible payload of superframes on the bus links. A node is configured to: determine that the node has a transmit token; transmit an Ethernet frame within a tunnel on the full-duplex bus links in at least one of an upstream direction towards a main-node or a downstream direction towards an end-sub-node; receive, while transmitting the Ethernet frame, a request for the transmit token from one or more other nodes in the tunnel on at least one of the full-duplex bus links in a direction opposite the Ethernet frame; and transmit the transmit token to a next node based on an order of priority of the one or more other nodes.

    SYNCHRONOUS, FULL DUPLEX DAISY-CHAINED COMMUNICATION SYSTEM
    2.
    发明申请
    SYNCHRONOUS, FULL DUPLEX DAISY-CHAINED COMMUNICATION SYSTEM 有权

    公开(公告)号：US20250088340A1

    公开(公告)日：2025-03-13

    申请号：US18464512

    申请日：2023-09-11

    Applicant: Analog Devices, Inc.

    Inventor： Martin KESSLER ,  Lewis F. LAHR ,  William HOOPER ,  Matthew PUZEY

    IPC: H04L5/14 ,  H04L7/00

    Abstract: A communication system includes a plurality of nodes connected in a daisy-chain via respective bus links, wherein the plurality of nodes are configured for full duplex, synchronized communication via a carrier-based modulation scheme over the bus links. A node is configured to: transmit a downstream synchronization control header (DnSCH) to a downstream node; receive an upstream synchronization response header (UpSRH) from the downstream node; measure a delay between the DnSCH and the UpSRH; send delay information to the downstream node in a DnSCH; receive a time adjusted UpSRH; and communicate with the downstream node and any upstream node over frames based on the delay information. The frames may include a header; a flexible payload defined by a stream mapping that assigns a byte location within the flexible payload to a stream; and a footer.

    SYNCHRONOUS AUDIO COMMUNICATION AND BUS POWER OVER MULTI-PAIR CABLES AND CONNECTORS
    3.
    发明公开
    SYNCHRONOUS AUDIO COMMUNICATION AND BUS POWER OVER MULTI-PAIR CABLES AND CONNECTORS 审中-公开

    公开(公告)号：US20240004446A1

    公开(公告)日：2024-01-04

    申请号：US18346226

    申请日：2023-07-01

    Applicant: Analog Devices, Inc.

    Inventor： Martin KESSLER ,  Stuart PATTERSON

    IPC: G06F1/26 ,  G06F3/16

    CPC classification number: G06F1/26 ,  G06F3/162

    Abstract: In some examples of both networks and methods, a data communication network includes a plurality of nodes. The nodes include a main node (MN) and at least one sub node (SNi=SN0, . . . SNX). Each node includes a node transceiver. The node transceiver is operable to perform data communication in accordance with a first network protocol for power over data via a pair of conductors (e.g., the conductors of bus). A physical layer includes a cable segment (e.g., the cable segment of bus) between each node. Each cable segment includes a plurality of pairs of conductors (e.g., pairs) and a connector (e.g., 8P8C connector—though other connectors with multiple pairs of conductors can be used) at each end. A first pair of the conductors (e.g., connected to pin 4 and pin 5 of the 8P8C connector) implements the first network protocol between the nodes. One or more of the remaining pairs of the conductors provide supplemental power to the nodes 102.

    GPIO-TO-GPIO COMMUNICATION ON A MULTI-NODE DAISY-CHAINED NETWORK
    6.
    发明申请
    GPIO-TO-GPIO COMMUNICATION ON A MULTI-NODE DAISY-CHAINED NETWORK 审中-公开

    公开(公告)号：US20170220502A1

    公开(公告)日：2017-08-03

    申请号：US15411846

    申请日：2017-01-20

    Applicant: Analog Devices, Inc.

    Inventor： Martin KESSLER ,  William HOOPER ,  Lewis F. LAHR

    IPC: G06F13/364 ,  G06F13/40 ,  G06F13/42

    CPC classification number: G06F13/364 ,  G06F13/404 ,  G06F13/4282

    Abstract: Disclosed herein are systems and techniques for general purpose input/output (GPIO)-to-GPIO communication in a multi-node, daisy-chained network. In some embodiments, a transceiver may support GPIO between multiple nodes, without host intervention after initial programming. In some such embodiments, the host may be required only for initial setup of the virtual ports. In some embodiments, GPIO pins can be inputs (which may change virtual ports) or outputs (which may reflect virtual ports). In some embodiments, multiple virtual ports may be mapped to one GPIO output pin (with the values OR'ed together, for example). In some embodiments, multiple GPIO input pins may be mapped to one virtual port. For example, multiple GPIO input pin values may be OR'ed together, even if they come from multiple nodes.

    TWO-WIRE COMMUNICATION SYSTEMS AND APPLICATIONS
    8.
    发明申请
    TWO-WIRE COMMUNICATION SYSTEMS AND APPLICATIONS 有权

    公开(公告)号：US20220156219A1

    公开(公告)日：2022-05-19

    申请号：US17589715

    申请日：2022-01-31

    Applicant: Analog Devices, Inc.

    Inventor： Martin KESSLER ,  Miguel A. CHAVEZ ,  Lewis F. LAHR ,  William HOOPER ,  Robert Adams ,  Peter SEALEY

    IPC: G06F13/42 ,  G05B19/418 ,  G06F1/26 ,  H04B3/54 ,  G05B19/042 ,  H04L12/403 ,  G06F13/364

    Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

    SERIAL DAISY-CHAINED BUS POWER FOR SERIAL DAISY-CHAINED COMMUNICATION SYSTEM
    9.
    发明公开
    SERIAL DAISY-CHAINED BUS POWER FOR SERIAL DAISY-CHAINED COMMUNICATION SYSTEM 审中-公开

    公开(公告)号：US20240004825A1

    公开(公告)日：2024-01-04

    申请号：US18346214

    申请日：2023-07-01

    Applicant: Analog Devices, Inc.

    Inventor： Martin KESSLER

    IPC: G06F13/42

    CPC classification number: G06F13/4282 ,  G06F2213/0002

    Abstract: A network includes nodes. The nodes include a main node (MN) and a plurality of sub nodes (SNi=SN0, . . . SNX). Each node includes a node transceiver that is operable to perform data communication in accordance with a first network protocol. Each node transceiver includes and a positive power contact (V+) and a negative power contact (V−) operable to power the node transceiver to perform the data communication. The data communication network includes a two conductor combined power and data physical layer/medium. The physical layer connects the SN0 V+ to a bus power source positive power contact (VS+) in a first conductive path. The physical layer connects the MN V− and SNX V− to the bus power source negative power contact (VS−) in a second conductive path. The physical layer connects each SNi V−, for i=0 to X−1, to the SNi+1 V+ in the first conductive path.

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